Datasheet

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SLUS486B − AUGUST 2001 − REVISED JULY 2003

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APPLICATION INFORMATION

selection of MOSFETs

The peak current rating of a driver imposes a limit on the maximum gate charge of the external power MOSFET

driven by it. The limit is based on the amount of time needed to deliver or remove the required charge to achieve

the desired switching speed during turn-on and turn-off of the external transistor. Hence, there are the families

of gate driver circuits with different current ratings.

To demonstrate this, assume a constant time interval for the switching transition and a fixed gate drive

amplitude. A larger MOSFET with more gate charge will require higher current capability from the driver to

turn-on or turn-off the device in the same amount of time. Accordingly, there is a practical upper limit on gate

charge which can be driven by the UCC27222 family of drivers. Considering the current capability of the

TrueDrive output stage and the available dynamic range (delay adjust range) of the Predictive Gate Drive

circuitry, this limit is approximately 120 nC of gate charge.

Some higher current applications require several MOSFETs to be connected parallel and driven by the same

gate drive signal. If their combined gate charge exceeds 120 nC, the rise and fall times of the gate drive signals

will extend and limit the delay adjust range of the PGD circuit in the UCC27222. This may limit the benefits of

the PGD technology under certain operating conditions.

Note that there are additional considerations in the gate drive circuit design which influence the maximum gate

charge of the external MOSFETs. The most significant of these is the operating frequency which, together with

the amount of gate charge, will define the power dissipation in the driver. The allowable power dissipation is a

function of the maximum junction and operating temperatures, thermal and reliability considerations.

selection of bypass capacitor C2

C2 supplies the peak current required to turn on the Q2 synchronous rectifier MOSFET, as well as the peak

current to charge the C1 capacitor through the bootstrap diode. Since the synchronous MOSFET is turned on

with 0 V across its drain-to-source, there is no Miller, or gate-to-drain charge. Therefore the synchronous

MOSFET gate can be modeled as a simple linear capacitance. The value of this capacitance can be found from

the datasheet’s gate charge curve. Referring to Figure 5, the slope of the curve past the Miller plateau indicates

the equivalent gate capacitance. Because the Y-axis is described in volts, the capacitance is actually the inverse

of the slope of the curve. For example, the curve in Figure 4 has a slope of approximately 2 V / 12 nC over the

gate charge range of 10 nC to 40 nC. The equivalent capacitance is 12 nC / 2 V = 6 nF. With the equivalent

capacitance, the minimum bypass capacitor value can be calculated as:

MIN

where

 C

is the equivalent gate capacitance,

 k is the voltage ripple on C2, expressed as a percentage

For a peak-to-peak ripple of 3%, the minimum C2 capacitor value is calculated to be 200 nF. A 220-nF capacitor

would be used in this case.

(2)