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UC28023

UC28025

SLUS557F -- MARCH 2003 -- REVISED AUGUST 2010

ECONOMY HIGH-SPEED PWM CONTROLLER

www.ti.com

FEATURES

D Peak Current Mode, Average Current Mode,

or Voltage Mode (with Feed-Forward) Control

Methods

D Practical Operation Up to 1 MHz

D 50-ns Propagation Delay to Output

D ±1.5-A Peak Totem Pole Outputs

D 9-V to 30-V Nominal Operational Voltage

Range

D Wide Bandwidth Error Amplifier

D Fully Latched Logic with Double Pulse

Suppression

D Pulse-by-Pulse Current Limiting

D Programmable Maximum Duty Cycle Control

D Under--Voltage Lockout with Hysteresis

D Trimmed 5.1-V Reference with UVLO

D Same Functionality as UC3823 and UC3825

APPLICATIONS

D Off-Line and DC/DC Power Supplies

D Converters Using Voltage Mode, Peak

Current Mode, or Average Current Mode

Control Methods

D Single-Ended or Two-Switch Topology

Designs

DESCRIPTION

The UC28023 and UC28025 are fixed-frequency

PWM controllers optimized for high-frequency

switched-mode power supply applications. The

UC28023 is a single output PWM for single-ended

topologies while the UC28025 offers dual

alternating outputs for double-ended and full

bridge topologies.

Targeted for cost effective solutions with minimal

external components, UC2802x include an

oscillator, a temperature compensated reference,

a wide band width error amplifier, a high-speed

current-sense comparator and high-current

active-high totem-pole outputs to directly drive

external MOSFETs.

Protection circuitry includes a current limit

comparator with a 1-V threshold, a TTL

compatible shutdown port, and a soft-start pin

which will double as a maximum duty cycle clamp.

The logic is fully latched to provide jitter free

operation and prohibit multiple pulses at an

output. An undervoltage lockout section with

800 mV of hysteresis assures low start-up

current. During undervoltage lockout, the outputs

are high impedance. Particular care was given to

minimizing propagation delays through the

comparators and logic circuitry while maximizing

bandwidth and slew rate of the error amplifier.

Devices are available in the industrial temperature

range of --40°C to 105°C. Package offerings are

16-pin SOICW (DW), or 16-pin PDIP (N)

packages.

ORDERING INFORMATION

OUTPUT E

TERN

L CURRENT

PACKAGED DEVICES

CONFIGURATION

LIMIT REFERENCE

PDIP-16 (N) SOICW--16 (DW)

Single Yes UC28023N UC28023DW

-- 4 0 °C to 105°C

Dual Alternating No UC28025N UC28025DW

(1)

The DW package are also available taped and reeled. Add an R suffix to the device type (i.e., UC28023DWR (2,000 devices per reel).

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Summary of content (19 pages)

PAGE 1
UC28023 UC28025 SLUS557F -- MARCH 2003 -- REVISED AUGUST 2010 ECONOMY HIGH-SPEED PWM CONTROLLER FEATURES D Peak Current Mode, Average Current Mode, D D D D D D D D D D D DESCRIPTION The UC28023 and UC28025 are fixed-frequency PWM controllers optimized for high-frequency switched-mode power supply applications. The UC28023 is a single output PWM for single-ended topologies while the UC28025 offers dual alternating outputs for double-ended and full bridge topologies.
PAGE 2
UC28023 UC28025 SLUS557F -- MARCH 2003 -- REVISED AUGUST 2010 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted(1) UC28023 Input voltage range, UC28025 UNIT VC, VCC VC, VCC 30 V Output current, IOUT(DC) OUT OUTA, OUTB ±0.
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UC28023 UC28025 SLUS557F -- MARCH 2003 -- REVISED AUGUST 2010 UC28023 N PACKAGE (TOP VIEW) INV NI EAOUT CLOCK RT CT RAMP SS 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 UC28023 DW PACKAGE (TOP VIEW) VREF VCC OUT VC PGND ILIMREF GND ILIM/SD 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VREF VCC OUT VC PGND ILIMREF GND ILIM/SD UC28025 DW PACKAGE (TOP VIEW) UC28025 N PACKAGE (TOP VIEW) INV NI EAOUT CLOCK RT CT RAMP SS INV NI EAOUT CLOCK RT CT
PAGE 4
UC28023 UC28025 SLUS557F -- MARCH 2003 -- REVISED AUGUST 2010 ELECTRICAL CHARACTERISTICS TA = --40°C to 105°C , TJ = TA, RT = 3.65 kΩ, CT = 1 nF, VCC = 15 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 5.05 V REFERENCE VREF Reference voltage TJ = 25°C, 5.10 5.
PAGE 5
UC28023 UC28025 SLUS557F -- MARCH 2003 -- REVISED AUGUST 2010 ELECTRICAL CHARACTERISTICS TA = --40°C to 105°C , TJ = TA, RT = 3.65 kΩ, CT = 1 nF, VCC = 15 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX 20 UNIT SOFT-START ICHG Charge current VSS = 0.5 V 3 9 IDISCHG Discharge current VSS = 1.0 V 1.0 7.5 μA mA CURRENT LIMIT/SHUTDOWN ILIMIT Current limit bias current ILIMIT Offset voltage UC28023 0 V < V(ILIM/SD) < 4 V ILIMREF Common mode range(1) UC28023 1.
PAGE 6
UC28023 UC28025 SLUS557F -- MARCH 2003 -- REVISED AUGUST 2010 FUNCTIONAL BLOCK DIAGRAM CLOCK 4 UC28025 RT 5 CT 6 EAOUT 3 NI 2 INV 1 11 OUTA PWM Latch + 1.25 V RAMP 7 13 VC Toggle F/F OSCILLATOR T R 14 OUTB SD Wide Bandwidth Error Amplifier 12 PGND VIN + 9 μA UC28023 Inhibit 13 VC 14 OUT SS 8 ILIMREF 11 (UC28023 Only) 1V (UC28025 Only) 1V 12 PGND ILIM Comparator Shutdown Comparator ILIM/SD 9 Internal Bias 1.
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UC28023 UC28025 SLUS557F -- MARCH 2003 -- REVISED AUGUST 2010 TERMINAL FUNCTIONS NAME TERMINAL I/O DESCRIPTION UC28023 UC28025 CLOCK 4 4 O Output of the internal oscillator CT 6 6 I Timing capacitor connection pin for oscillator frequency programming. The timing capacitor should be connected to the device ground using minimal trace length. EAOUT 3 3 O Output of the error amplifier for compensation GND 10 10 -- Analog ground return pin.
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UC28023 UC28025 SLUS557F -- MARCH 2003 -- REVISED AUGUST 2010 APPLICATION INFORMATION + VIN 42 V to 56 V -- VOUT 5 V 1 A to 10 A 12 V + 0.1 μF 15 13 VCC VC 16 VREF 4.7 μF 15 V OUTB 14 -5:1 1Ω OUTA 11 4.3 kΩ 10 kΩ UC28025 1 INV 6 μF 1 kΩ 1N 5820 2 NI 0.8 μH 4.7 μF 1 kΩ ILIM/SD 9 1 nF 22 pF 3.3 kΩ 3 EAOUT RAMP 7 8.2 kΩ 10 nF 4 CLOCK 5 RT 1.5 kΩ CT 6 PGND 12 GND SS 10 8 1 kΩ 120 pF CT 470 pF 0.1 μF UDG--03047 Figure 1. Typical Application: 1.
PAGE 9
UC28023 UC28025 SLUS557F -- MARCH 2003 -- REVISED AUGUST 2010 APPLICATION INFORMATION PCB LAYOUT CONSIDERATIONS High speed circuits demand careful attention to layout and component placement. To assure proper performance of the UC2802x follow these rules: 1. Use a ground plane. 2. Damp or clamp parasitic inductive kick energy from the gate of driven MOSFETs. Do not allow the output pins to ring below ground. A series gate resistor or a shunt 1-A Schottky diode at the output pin serves this purpose. 3.
PAGE 10
UC28023 UC28025 SLUS557F -- MARCH 2003 -- REVISED AUGUST 2010 APPLICATION INFORMATION GAIN AND PHASE vs FREQUENCY 100 VOLTAGE vs TIME 5 VIN GAIN 60 AV -- Gain -- dB VSEAout -- E/A Output Voltage -- V 80 40 20 0 0 --20 --90 --40 100 1k 10 k 100 k 1M 10 M --180 100 M Phase -- ° PHASE 4 3 2 1 0 0.2 0.4 0.6 tdelay -- Delay Time-- μs fOSC -- Frequency -- Hz Figure 3. Open Loop Frequency Response VOUT 0.8 1.0 Figure 4.
PAGE 11
UC28023 UC28025 SLUS557F -- MARCH 2003 -- REVISED AUGUST 2010 APPLICATION INFORMATION OSCILLATOR IR 10.0 UC2802x RT 3 kΩ ≤ RT ≤ 100 kΩ 5 4.70 3V IC = IR 2.20 TD -- Dead Time -- μs CT 6 5.1 V CLOCK 4 DEAD TIME vs TIMING CAPACITANCE 1.00 0.47 0.22 Blanking 0.10 TD 400 μA 0.047 0.47 UDG--03052 2.2 4.7 10.0 22.0 47 CT -- Timing Capacitance -- nF 100 Figure 8. Figure 7. Oscillator Circuit TIMING RESISTANCE vs FREQUENCY 100 k 1.0 160 DEAD TIME vs FREQUENCY 4.
PAGE 12
UC28023 UC28025 SLUS557F -- MARCH 2003 -- REVISED AUGUST 2010 APPLICATION INFORMATION SYNCHRONIZATION Figure 11 shows a generalized synchronization. Figure 12 shows a synchronozed operation of two units in close proximity. UC2802x (Master) UC2802x (Slave) VREF 16 RT 1.15 Ω 10 μF CLOCK 43 Ω 0.1 μF 43 Ω 0.1 μF 5 CT CT RT 6 CT 2N222 4 RT RT 5 6 43 Ω Local Ramp 0.1 μF 24 Ω CT To other slaves 24 Ω Local Ramp 470 Ω UDG--03050 Figure 11.
PAGE 13
UC28023 UC28025 SLUS557F -- MARCH 2003 -- REVISED AUGUST 2010 APPLICATION INFORMATION FEEDFORWARD CIRCUIT VIN UC2802x RFF CFF 7 RAMP 4 CLOCK 6 CT 5 RT UDG--03050 Figure 13. Feedforward Technique for Off-Line Voltage-Mode Applications CONSTANT VOLT-SECOND CLAMP CIRCUIT The circuit for the UC28023 shown in Figure 14 describes achievement a constant volt-second product clamp over varying input voltages.
PAGE 14
UC28023 UC28025 SLUS557F -- MARCH 2003 -- REVISED AUGUST 2010 The circuit for the UC28025 shown in Figure 15 describes achievement a constant volt-second product clamp over varying input voltages. The ramp generator components, RT and CR are chosen so that the ramp at Pin 9 (ILIM/SD) crosses the 1-V threshold at the same time the desired maximum volt-second product is reached.
PAGE 15
UC28023 UC28025 SLUS557F -- MARCH 2003 -- REVISED AUGUST 2010 APPLICATION INFORMATION OUTPUTS UC28023 has one output and UC28025 has dual alternating outputs. UC2802x SATURATION VOLTAGE vs OUTPUT CURRENT 3 15 VCC VSAT -- Saturation Voltage -- V 13 VC OUTx 2 Source 1 12 PWRGND Sink 10 GND 0 0 0.25 Figure 16. Simplified Schematic --0.2 10 5 40 80 120 160 tRISE (tFALL) -- Time -- ns CLOAD = 10 nF 0.2 0 200 15 ILOAD -- Load Current -- A VOUT -- Output Voltage -- V 0 0 1.
PAGE 16
UC28023 UC28025 SLUS557F -- MARCH 2003 -- REVISED AUGUST 2010 APPLICATION INFORMATION Open Loop Laboratory Test Fixture The following test fixture is useful for exercising many of the UC28025’s functions and measuring their specifications. As with any wideband circuit, careful ground and by-pass procedures should be followed. The use of a ground plane is highly recommended. UC28025 0.1 μF VCC 15 4 CLOCK RT 3.65 kΩ 5 RT 0.1 μF 6 CT 200 Ω 3 EAOUT 27 kΩ 50 Ω 10 kΩ 4.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 24-Jan-2013 Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
PAGE 19
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