Datasheet

PRINCIPLES OF OPERATION
Applications
Architecture
V
CCA
A
V
CCB
One-Shot
One-Shot
N1
P1
R1
R2
Translator
One-Shot
One-Shot
N2
OS1
OS2
OS4
OS3
T2
T1
RpubRpua
Bias
Npass
B
P2
Translator
TXS0108E
SCES642B – DECEMBER 2007 – REVISED SEPTEMBER 2008 ..................................................................................................................................... www.ti.com
The TXS0108E can be used in level-translation applications for interfacing devices or systems operating at
different interface voltages with one another. The TXS0108E is ideal for use in applications where an open-drain
driver is connected to the data I/Os. The TXS0108E can also be used in applications where a push-pull driver is
connected to the data I/Os, but the TXB0104 might be a better option for such push-pull applications. The
TXS0108E device is a semi-buffered auto-direction-sensing voltage translator design is optimized for translation
applications (e.g. MMC Card Interfaces) that require the system to start out in a low-speed open-drain mode and
then switch to a higher speed push-pull mode.
To address these application requirements, a semi-buffered architecture design is used and is illustrated below
(see Figure 1 ). Edge-rate accelerator circuitry (for both the high-to-low and low-to-high edges), a High-Ron
n-channel pass-gate transistor (on the order of 300 Ω to 500 Ω ) and pull-up resistors (to provide DC-bias and
drive capabilities) are included to realize this solution. A direction-control signal (to control the direction of data
flow from A to B or from B to A) is not needed. The resulting implementation supports both low-speed open-drain
operation as well as high-speed push-pull operation.
Figure 1. Architecture of a TXS01xx Cell
When transmitting data from A to B ports, during a rising edge the One-Shot (OS3) turns on the PMOS transistor
(P2) for a short-duration and this speeds up the low-to-high transition. Similarly, during a falling edge, when
transmitting data from A to B, the One-Shot (OS4) turns on NMOS transistor (N2) for a short-duration and this
speeds up the high-to-low transition. The B-port edge-rate accelerator consists of one-shots OS3 and OS4,
Transistors P2 and N2 and serves to rapidly force the B port high or low when a corresponding transition is
detected on the A port.
When transmitting data from B to A ports, during a rising edge the One-Shot (OS1) turns on the PMOS transistor
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Product Folder Link(s): TXS0108E