Datasheet

Host
Processor
I C
2
VBUS
Data
I C Registers
2
00h
E0h
E1h
VBUS
Address
E8h
EAh
FFh
VBUS[23:0]
Line Mode
VBUS Registers
00 0000h
FIFO
VPS/Gemstar
VITC
WSS/CGMS
CC
80 051Ch
80 0520h
80 052Ch
80 0600h
80 0700h
90 1904h
FF FFFFh
TVP5160
www.ti.com SLES135E–FEBRUARY 2005–REVISED APRIL 2011
2.9.2 I
2
C Operation
Data transfers occur utilizing the following formats.
Read from I
2
C control registers
receive
S 10111000 ACK subaddress ACK S 10111001 ACK NAK P
data
Write to I
2
C control registers
S 10111000 ACK subaddress ACK send data ACK P
S = I
2
C bus start condition
P = I
2
C bus stop condition
ACK = Acknowledge generated by the slave
NAK = Acknowledge generated by the master, for multiple byte read master will ACK each
byte except the last byte
Subaddress = Subaddress byte
Data = Data byte
I
2
C bus address = In the example shown, I2CA0/I2CA1 are in default mode. Write (B8h), Read (B9h)
2.9.3 VBUS Access
The TVP5160 decoder has additional internal registers accessible through an indirect access to an
internal 24-bit address wide VBUS. Figure 2-13 shows the VBUS registers access.
Figure 2-13. VBUS Access
Copyright © 2005–2011, Texas Instruments Incorporated Functional Description 33
Submit Documentation Feedback
focus.ti.com: TVP5160