Datasheet

CbCr[9:0] Cb
SCLK
Cr Cb Cr Cb0 Cr0 Cb1 Cr1
0
HS Start
Horizontal Blanking
HS
HS Stop
A C
B
AVID
D
NOTE: AVID rising edge occurs 4 clock cycles early.
Y[9:0]
Y Y Y Y Y0 Y1 Y2 Y3Horizontal Blanking
AVID Stop AVID Start
TVP5160
SLES135E–FEBRUARY 2005–REVISED APRIL 2011 www.ti.com
NOTE: AVID rising edge occurs 4 clock cycles early.
Figure 2-10. Horizontal Synchronization Signals for 20-Bit 4:2:2 Mode
SCLK = 1X PIXEL CLOCK
(1)
MODE A B C D
NTSC 601 53 64 19 138
PAL 601 56 64 22 144
480p 53 64 19 138
576p 56 64 22 144
(1) 20-bit 4:2:2 timing with 1× pixel clock reference 601 = ITU-R BT.601 timing
30 Functional Description Copyright © 2005–2011, Texas Instruments Incorporated
Submit Documentation Feedback
focus.ti.com: TVP5160