Datasheet
TUSB7320, TUSB7340
SLLSE76E–MARCH 2011– REVISED JULY 2011
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Table 4-40. MSI Message Control Register Description
Bit Field Name Access Description
15:8 RSVD r Reserved. Returns zeros when read.
Per-vector Masking Capable. This bit is read only 0 indicating that the
8 PVM_CAP r
TUSB73X0 does not support per-vector masking.
64 Bit Message Capability. This bit is read only 1 indicating that the
7 64CAP r
TUSB73X0 supports 64 bit MSI message addressing.
Multiple Message Enable. This bit indicates the number of distinct
messages that the TUSB73X0 is allowed to generate.
000 – 1 Message (All interrupters mapped to the same message)
001 – 2 Messages (Interrupters 0, 2, 4, and 6 mapped to message 0 and
Interrupters 1, 3, 5, and 7 mapped to message 1)
010 – 4 Messages (Interrupters 0 and 4 mapped to message 0,
6:4 MM_EN rw
Interrupters 1 and 5 mapped to message 1, Interrupters 2 and 6 mapped
to message 2, Interrupters 3 and 7 mapped to message 3)
011 – 8 Messages (Interrupter # mapped to corresponding message #)
100 – 16 Messages (Interrupter # mapped to corresponding message #)
101 – 32 Messages (Interrupter # mapped to corresponding message #)
110 – Reserved111 – Reserved
Multiple Message Capabilities. This field indicates the number of distinct
3:1 MM_CAP r messages that TUSB73X0 is capable of generating. This field is read
only ‘011’ indicating that the TUSB73X0 can signal 8 distinct messages.
MSI Enable. This bit is used to enable MSI interrupt signaling. MSI
signaling must be enabled by software for the TUSB73X0 to signal an
0 MSI_EN rw MSI
0 – MSI signaling is prohibited
1 – MSI signaling is enabled
4.31 MSI Lower Message Address Register
This register contains the lower 32 bits of the address that a MSI message is written to when an interrupt
is to be signaled.
PCI register offset: 4Ch
Register type:Read/Write
Default value: 0000 0000h
Table 4-41. PCI Register 4Ch
Bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
No.
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
State
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
No.
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
State
Table 4-42. MSI Lower Message Address Register Description
Bit Field Name Access Description
31:2 ADDRESS rw System Specified Message Address
1:0 RSVD r Reserved. Return zeros when read.
42 CLASSIC PCI CONFIGURATION SPACE Copyright © 2011, Texas Instruments Incorporated
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Product Folder Link(s): TUSB7320 TUSB7340