Datasheet

TUSB7320, TUSB7340
SLLSE76E–MARCH 2011– REVISED JULY 2011 www.ti.com
4.13 Base Address Register 2
This register is used to program the memory address used to access the MSI-X Table and PBA.
PCI register offset: 18h
Register type:Read/Write, Read-only
Default value: 0000 0004h
Table 4-18. PCI Register 18h
Bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
No.
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
State
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
No.
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0
State
Table 4-19. Base Address Register 2 Description
Bit Field Name Access Description
Memory Address. The lower 32 bits of the 64-bit memory address field
31:20 ADDRESS rw for the TUSB73X0 uses 19 read/write bits indicating that 8 MB of
memory space is required.
19:4 RSVD r Reserved. These bits are read-only and returns zeros when read.
Pre-fetchable. This bit is read only 0 indicating that this memory window
3 PRE_FETCH r
is not prefetchable.
Memory Type. This field is read only 10b indicating that this window can
2:1 MEM_TYPE r
be located anywhere in the 64-bit address space.
Memory Space Indicator. This field returns 0 indicating that memory
0 MEM_IND r
space is used.
4.14 Base Address Register 3
This register is used to program the memory address used to access the MSI-X Table and PBA.
PCI register offset: 1Ch
Register type:Read/Write
Default value: 0000 0000h
Table 4-20. PCI Register 1Ch
Bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
No.
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
State
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
No.
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
State
Table 4-21. Table 9‑3 Base Address Register 3 Description
Bit Field Name Access Description
Memory Address. This field indicates the upper 32 bits of the 64-bit
31:0 ADDRESS rw
memory address for the TUSB73X0.
36 CLASSIC PCI CONFIGURATION SPACE Copyright © 2011, Texas Instruments Incorporated
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