Datasheet

TUSB7320, TUSB7340
www.ti.com SLLSE76E–MARCH 2011– REVISED JULY 2011
Table 5-11. Bit Descriptions – Correctable Error Severity Register
(1)
(continued)
Receiver Error. This bit is asserted when an 8b/10b error is detected by
0† RX_ERROR † rcu
the PHY at any time.
5.8 correctable Error Mask Register
The Correctable Error Status Register reports the status of individual errors as they occur. Software may
clear these bits only by writing a 1 to the desired location.
PCI Express Extended Register Offset: 114h
Register type:Read-Only, Read/Write
Default value: 0000 2000h
Table 5-12. PCI Express Extended Register 114h
Bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
No.
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
State
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
No.
Reset
0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0
State
Table 5-13. Bit Descriptions – Correctable Error Mask Register
(1)
Bit Field Name Access Description
31:14 RSVD r Reserved. Returns zeros when read.
Advisory Non-Fatal Error Mask.
13† ANFEM † rw 0 – Error Condition is Unmasked
1 – Error Condition is Masked
Replay Timer Timeout Mask.
12† REPLAY_TMOUT_MASK † rw 0 – Error Condition is Unmasked
1 – Error Condition is Masked
11:9 RSVD r Reserved. Returns zeros when read.
REPLAY_NUM Rollover Mask.
8† REPLAY_ROLL_MASK † rw 0 – Error Condition is Unmasked
1 – Error Condition is Masked
Bad DLLP Error Mask.
7† BAD_DLLP_MASK † rw 0 – Error Condition is Unmasked
1 – Error Condition is Masked
Bad TLP Error Mask.
6† BAD_TLP_MASK † rw 0 – Error Condition is Unmasked
1 – Error Condition is Masked
5:1 RSVD r Reserved. Returns zeros when read.
Receiver Error Mask.
0† RX_ERROR_MASK † rw 0 – Error Condition is Unmasked
1 – Error Condition is Masked
(1) Bits marked with † are reset by a PCI Express reset (PERST#), a GRST#, or the internally-generated power-on reset
Copyright © 2011, Texas Instruments Incorporated PCI EXPRESS EXTENDED CONFIGURATION SPACE 71
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Product Folder Link(s): TUSB7320 TUSB7340