Datasheet

TUSB7320, TUSB7340

SLLSE76E–MARCH 2011– REVISED JULY 2011

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Figure 3-6. Serial-Bus Protocal - Byte Write

Figure 3-7 illustrates a single byte read. The host controller issues a start condition and sends the 7-bit

slave device address and the R/W command bit is equal to 0b (write). The slave device acknowledges if it

recognizes the slave address. Next, the EEPROM word address is sent by the host controller, and another

slave acknowledgment is expected. Then, the host controller issues a restart condition followed by the

7-bit slave address and the R/W command bit is equal to 1b (read). Once again, the slave device

responds with an acknowledge. Next, the slave device sends the 8-bit data byte, MSB first. Since this is a

1-byte read, the host controller responds with no acknowledge (logic high) indicating the last data byte.

Finally, the host controller issues a stop condition.

Figure 3-7. Serial-Bus Protocal - Byte Read

Figure 3-8 illustrates the serial interface protocol during a multi-byte serial EEPROM download. The

serial-bus protocol starts exactly the same as a 1-byte read. The only difference is that multiple data bytes

are transferred. The number of transferred data bytes is controlled by the host controller master. After

each data byte, the host controller master issues acknowledge (logic low) if more data bytes are

requested. The transfer ends after a host controller master no acknowledge (logic high) followed by a stop

condition.

Figure 3-8. Serial-Bus Protocal - Multibyte Read

Bit 7 (PROT_SEL) in the serial-bus control and status register changes the serial-bus protocol. Each of

the three previous serial-bus protocol figures illustrates the PROT_SEL bit default (logic low). When this

control bit is asserted, the word address and corresponding acknowledge are removed from the serial-bus

protocol. This feature allows the system designer a second serial-bus protocol option when selecting

external EEPROM devices.

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Product Folder Link(s): TUSB7320 TUSB7340