Datasheet


    
SLLS363A − SEPTEMBER 1999 − REVISED NOVEMBER 2000
38
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
transmit (continued)
The sequence of events for a normal packet transmission is as follows:1
a. Transmit operation initiated. The PHY asserts grant on the CTL lines followed by idle to hand over
control of the interface to the link so that the link may transmit a packet. The PHY releases control of
the interface (i.e., it 3-states the CTL and D outputs) following the idle cycle.
b. Optional idle cycle. The link may assert at most one idle cycle preceding assertion of either hold or
transmit. This idle cycle is optional; the link is not required to assert idle preceding either hold or transmit.
c. Optional hold cycles. The link may assert hold for up to 47 cycles preceding assertion of transmit. These
hold cycle(s) are optional; the link is not required to assert hold preceding transmit.
d. Transmit data. When data is ready to be transmitted, the link asserts transmit on the CTL lines along
with the data on the D lines.
e. Transmit operation terminated. The transmit operation is terminated by the link asserting hold or idle
on the CTL lines. The link asserts hold to indicate that the PHY is to retain control of the serial bus in
order to transmit a concatenated packet. The link asserts idle to indicate that packet transmission is
complete and the PHY may release the serial bus. The link then asserts idle for one more cycle following
this cycle of hold or idle before releasing the interface and returning control to the PHY.
f. Concatenated packet speed-code. If multispeed concatenation is enabled in the PHY, the link shall
assert a speed-code on the D lines when it asserts hold to terminate packet transmission. This
speed-code indicates the transmission speed for the concatenated packet that is to follow. The
encoding for this concatenated packet speed-code is the same as the encoding for the received packet
speed-code (see Table 20. The link may not concatenate an S100 packet onto any higher-speed
packet.
g. After regaining control of the interface, the PHY shall assert at least one cycle of idle before any
subsequent status transfer, receive operation, or transmit operation.
00
00 0000
(e)(d)(c)(b)(a)
01
00
000011
D0–D7
CTL0, CTL1
SYSCLK
00
Link controls CTL and D
PHY High-Impedance CTL and D outputs
Figure 21. Cancelled/Null packet Transmission