Datasheet

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SLLS363A − SEPTEMBER 1999 − REVISED NOVEMBER 2000
14
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
SYSCLK
Dx, CTLx
t
d
Figure 3. Dx and CTLx Output Delay Relative to SYSCLK Waveforms
APPLICATION INFORMATION
internal register configuration
There are 16 accessible internal registers in the TSB41LV06A. The configuration of the registers at addresses
0 through 7 (the base registers) is fixed, while the configuration of the registers at addresses 8h through Fh (the
paged registers) is dependent upon which one of eight pages, numbered 0 through 7h, is currently selected.
The selected page is set in base register 7h.
The configuration of the base registers is shown in Table 1 and corresponding field descriptions given in Table 2.
The base register field definitions are unaffected by the selected page number.
A reserved register or register field (marked as reserved or Rsvd in the register configuration tables below) is
read as 0, but is subject to future usage. All registers in pages 2 through 6 are reserved.
Table 1. Base Register Configuration
ADDRESS BIT POSITION
0 1 2 3 4 5 6 7
0000 Physical ID R CPS
0001 RHB IBR Gap_Count
0010 Extended (111b) Rsvd Num_Ports (0110b)
0011 PHY_Speed (010b) Rsvd Delay (0000b)
0100 L C Jitter (000b) Pwr_Class
0101 RPIE ISBR CTOI CPSI STOI PEI EAA EMC
0110 Reserved
0111 Page_Select Rsvd Port_Select