Datasheet

TPA2+
TPA2-
TPB2+
TPB2-
TPA1+
TPA1-
TPB1+
TPB1-
TPB0+
TPB0-
Cable Port 0
Cable Port 1
Cable Port 2
CPS
LPS
SLPEN
PINT
LCLK_PMC
LREQ
CTL0
CTL1
D0
D5
D1
D2
D3
D4
D6
D7
RESET
S5_LKON
PD
BMODE
Link
Interface
I/O
Received Data
Decoder/Retimer
Arbitration
and Control
State Machine
Logic
Transmit
Data
Encoder
Crystal Oscillator,
PLL System,
and Transmit
Clock Generator
PCLK
S2_PC0
S1_PC1
S0_PC2
SE
SM
S3
S4
TESTM
VREG_PD
Voltage
Regulator
XI
TPA0+
TPA0-
Bias Voltage
and
Current
Generator
R0
R1
TPBIAS0_SD0
TPBIAS1_SD1
TPBIAS2_SD2
XO
TSB41BA3D
SLLS959A – DECEMBER 2008 – REVISED MARCH 2009 ............................................................................................................................................... www.ti.com
FUNCTIONAL BLOCK DIAGRAM
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