Datasheet
TSB41BA3D
SLLS959A – DECEMBER 2008 – REVISED MARCH 2009 ...............................................................................................................................................
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Table 5. Base Register Field Descriptions (continued)
FIELD SIZE TYPE DESCRIPTION
Num_Ports 4 Rd Number of ports. This field indicates the number of ports implemented in the PHY. For the TSB41BA3D,
this field is 3.
PHY_Speed 3 Rd PHY speed capability. This field is no longer used. For the TSB41BA3D PHY, this field is 111b. Speeds
for 1394b PHYs must be checked on a port-by-port basis.
SREN 1 Rd/Wr Standby/restore enable. This bit when set to 1 enables the port to go into the standby reduced power
state when commanded by a Standby PHY command packet. This enable works for all ports of the local
device. Note the 1394b standard only allows leaf (one port connected) nodes to be placed into standby
mode.
Delay 4 Rd PHY repeater data delay. This field indicates the worst-case repeater data delay of the PHY, expressed
as 144+(delay × 20) ns. For the TSB41BA3D, this field is Fh. The worst-case repeater delay for S100B is
538 ns.
LCtrl 1 Rd/Wr
Link-active status control. This bit controls the indicated active status of the LLC reported in the self-ID
packet. The logical AND of this bit and the LPS active status is replicated in the L field (bit 9) of the
self-ID packet. The LLC bit in the node self-ID packet is set active only if both the LPS input is active and
the LCtrl bit is set.
The LCtrl bit provides a software-controllable means to indicate the LLC self-ID active status in lieu of
using the LPS input terminal.
The LCtrl bit is set to 1 by hardware reset and is unaffected by bus reset.
NOTE: The state of the PHY-LLC interface is controlled solely by the LPS input, regardless of the state of
the LCtrl bit. If the PHY-LLC interface is operational as determined by the LPS input being active, then
received packets and status information continue to be presented on the interface, and any requests
indicated on the LREQ input are processed, even if the LCtrl bit is cleared to 0.
C 1 Rd/Wr Contender status. This bit indicates that this node is a contender for the bus or isochronous resource
manager. This bit is replicated in the c field (bit 20) of the self-ID packet. This bit is set to 0 on hardware
reset. After hardware reset, this bit can only be set via a software register write. This bit is unaffected by a
bus reset.
Jitter 3 Rd PHY repeater jitter. This field indicates the worst-case difference between the fastest and slowest
repeater data delay, expressed as (jitter+1) × 20 ns. For the TSB41BA3D, this field is 0.
Pwr_Class 3 Rd/Wr Node power class. This field indicates this node power consumption and source characteristics and is
replicated in the pwr field (bits 21 – 23) of the self-ID packet. This field is reset to the state specified by the
S5 – S0 input terminals on a hardware reset and is unaffected by a bus reset. See Table 2 and Table 12 .
WDIE 1 Rd/Wr Watchdog interrupt enable. This bit, if set to 1, enables the port event interrupt (PIE) bit to be set
whenever resume operations begin on any port, or when any of the CTOI, CPSI, or STOI interrupt bits
are set and the link interface is nonoperational. This bit is reset to 0 by hardware reset and is unaffected
by bus reset.
ISBR 1 Rd/Wr
Initiate short arbitrated bus reset. This bit, if set to 1, instructs the PHY to initiate a short (1.3 µ s)
arbitrated bus reset at the next opportunity. This bit is reset to 0 by a bus reset. It is recommended that
short bus reset is the only reset type initiated by software. IEC 61883-6 requires that a node initiate short
bus resets to minimize any disturbance to an audio stream.
NOTE: Legacy IEEE Std 1394-1995-compliant PHYs are not capable of performing short bus resets.
Therefore, initiation of a short bus reset in a network that contains such a legacy device results in a long
bus reset being performed.
CTOI 1 Rd/Wr
Configuration time-out interrupt. This bit is set to 1 when the arbitration controller times out during tree-ID
start and might indicate that the bus is configured in a loop. This bit is reset to 0 by hardware reset or by
writing a 1 to this register bit.
If the CTOI and WDIE bits are both set and the LLC is or becomes inactive, then the PHY activates the
S5_LKON output to notify the LLC to service the interrupt.
NOTE: If the network is configured in a loop, then only those nodes which are part of the loop generate a
configuration time-out interrupt. All other nodes instead time out waiting for the tree-ID and/or self-ID
process to complete and then generate a state time-out interrupt and bus reset. This bit is only set when
the bus topology includes 1394a nodes; otherwise, 1394b loop healing prevents loops from being formed
in the topology.
CPSI 1 Rd/Wr
Cable power status interrupt. This bit is set to 1 whenever the CPS input transitions from high to low,
indicating that cable power might be too low for reliable operation. This bit is reset to 1 by hardware reset.
It can be cleared by writing a 1 to this register bit.
If the CPSI and WDIE bits are both set and the LLC is or becomes inactive, then the PHY activates the
S5_LKON output to notify the LLC to service the interrupt.
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