Datasheet

DESCRIPTION/ORDERING INFORMATION
TSB41BA3D
SLLS959A – DECEMBER 2008 – REVISED MARCH 2009 ............................................................................................................................................... www.ti.com
The TSB41BA3D provides the digital and analog transceiver functions needed to implement a three-port node in
a cable-based IEEE 1394 network. Each cable port incorporates two differential line transceivers. The
transceivers include circuitry to monitor the line conditions as needed for determining connection status, for
initialization and arbitration, and for packet reception and transmission. The TSB41BA3D interfaces with a
link-layer controller (LLC), such as the TSB82AA2, TSB12LV21, TSB12LV26, TSB12LV32, TSB42AA4,
TSB42AB4, TSB12LV01B, or TSB12LV01C. It can also be connected via cable port to an integrated 1394 Link +
PHY layer such as the TSB43AB2.
The TSB41BA3D is powered by a single 3.3-V supply. The core voltage supply is supplied by an internal voltage
regulator to the PLLVDD-CORE and DVDD-CORE terminals. To protect the phase-locked loop (PLL) from noise,
the PLLVDD-CORE terminals must be separately decoupled from the DVDD-CORE terminals. The
PLLVDD-CORE terminals are decoupled with 1- µ F and smaller decoupling capacitors and the DVDD-CORE
terminals are separately decoupled with 1- µ F and smaller decoupling capacitors. The separation between
DVDD-CORE and PLLVDD-CORE must be implemented by separate power supply rails or planes.
The TSB41BA3D can be powered by dual supplies, a 3.3-V supply for I/O and a core voltage supply. The core
voltage supply is supplied to the PLLVDD-CORE and DVDD-CORE terminals to the requirements in the
recommended operating conditions section of this data sheet. The PLLVDD-CORE terminals must be separated
from the DVDD-CORE terminals, the PLLVDD-CORE terminals are decoupled with 1- µ F and smaller decoupling
capacitors and the DVDD-CORE terminals separately decoupled with 1- µ F and smaller decoupling capacitors.
The separation between DVDD-CORE and PLLVDD-CORE can be implemented by separate power supply rails,
or by a single power supply rail, where the DVDD-CORE and PLLVDD-CORE are separated by a filter network
to keep noise from the PLLVDD-CORE supply.
The TSB41BA3D requires an external 49.152-MHz crystal to generate a reference clock. The external clock
drives an internal PLL, which generates the required reference signal. This reference signal provides the clock
signals that control transmission of the outbound encoded information. A 49.152-MHz clock signal is supplied by
the PHY to the associated LLC for synchronization of the two devices and is used for resynchronization of the
received data when operating the PHY-link interface in compliance with the IEEE 1394a-2000 standard. A
98.304-MHz clock signal is supplied by the PHY to the associated LLC for synchronization of the two devices
when operating the PHY-link interface in compliance with the IEEE 1394b-2002 standard. The power-down (PD)
function, when enabled by asserting the PD terminal high, stops operation of the PLL.
Data bits to be transmitted through the cable ports are received from the LLC on 2, 4, or 8 parallel paths
(depending on the requested transmission speed and PHY-link interface mode of operation). They are latched
internally, combined serially, encoded, and transmitted at 98.304, 122.78, 196.608, 245.76, 393.216, or 491.52
Mbps (referred to as S100, S100B, S200, S200B, S400, or S400B speed, respectively) as the outbound
information stream.
The PHY-link interface can follow either the IEEE 1394a-2000 protocol or the IEEE 1394b-2002 protocol. When
using a 1394a-2000 LLC such as the TSB12LV26, the BMODE terminal must be deasserted. The PHY-link
interface then operates in accordance with the legacy 1394a-2000 standard. When using a 1394b LLC such as
the TSB82AA2, the BMODE terminal must be asserted. The PHY-link interface then conforms to the 1394b-2002
standard.
The cable interface can follow either the IEEE 1394a-2000 protocol or the 1394b protocol on all ports. The mode
of operation is determined by the interface capabilities of the ports being connected. When any of the three ports
is connected to a 1394a-2000-compliant device, the cable interface on that port operates in the 1394a-2000
data-strobe mode at a compatible S100, S200, or S400 speed. When a bilingual port is connected to a
1394b-compliant node, the cable interface on that port operates per the 1394b-2002 standard at S100B, S200B,
or S400B speed. The TSB41BA3D automatically determines the correct cable interface connection method for
the bilingual ports.
ORDERING INFORMATION
T
A
PACKAGE
(1)
ORDERABLE PART NUMBER TOP-SIDE MARKING
0 ° C to 70 ° C HTQFP – PFP TSB41BA3DPFP TSB41BA3D
– 40 ° C to 85 ° C HTQFP – PFP TSB41BA3DIPFP TSB41BA3DI
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package .
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Product Folder Link(s): TSB41BA3D