Datasheet

TSB41BA3D
SLLS959A – DECEMBER 2008 – REVISED MARCH 2009 ............................................................................................................................................... www.ti.com
Table 1. Terminal Functions (continued)
TERMINAL
I/O DESCRIPTION
PFP
NAME TYPE
NO.
S5_LKON CMOS 2 I/O
Port sleep/mode selection terminal 5 and link-on output. This terminal can be connected to
the link-on input terminal of the LLC through a 1-k Ω resistor if the link-on input is available
on the link layer.
On hardware reset this terminal, when used with the other Port Speed/Mode Selection
terminals, allows the user to select whether ports act like a 1394b bilingual port (terminal at
logic 0) or as a 1394a-2000-only port (terminal 1394b bilingual mode or high through a
1-k Ω or less resistor to enable 1394b bilingual mode or high through a 1-k Ω or less resistor
to enable 1394a-2000-only mode. A bus holder is built into this terminal. See Table 2 . A
bus holder is built into this terminal.
After hardware reset, this terminal is the link-on output, which notifies the LLC or other
power-up logic to power up and become active. The link-on output is a square wave signal
with a period of approximately 163 ns (8 PCLK cycles) when active. The link-on output is
otherwise driven low, except during hardware reset when it is high-impedance.
The link-on output is activated if the LLC is inactive (the LPS input inactive or the LCtrl bit
cleared) and when one of the following occurs:
a. The PHY receives a link-on PHY packet addressed to this node.
b. The PEI (port-event interrupt) register bit is 1.
c. Any of the CTOI (configuration-timeout interrupt),
CPSI (cable-power-status interrupt), or STOI (state-time-out interrupt) register bits is 1
and the RPIE (resuming-port interrupt enable) register bit is also 1.
d. The PHY is power-cycled and the power class is 0 through 4.
Once activated, the link-on output is active until the LLC becomes active (both the LPS
input active and the LCtrl bit set). The PHY also deasserts the link-on output when a
bus-reset occurs unless the link-on output is otherwise active because one of the interrupt
bits is set (that is, the link-on output is active due solely to the reception of a link-on PHY
packet).
In the case of power-cycling the PHY, the LKON signal must stop after 167 s if the
preceding conditions have not been met.
NOTE: If an interrupt condition exists which otherwise would cause the link-on output to be
activated if the LLC were inactive, then the link-on output is activated when the LLC
subsequently becomes inactive.
TESTM CMOS 78 I Test control input. This input is used in the manufacturing test of the TSB41BA3D. For
normal use this terminal must be pulled high through a 1-k Ω resistor to V
DD
.
TPA0 – Cable 45 I/O Port-0 twisted-pair differential-signal terminals. Board traces from each pair of positive and
TPA0+ 46 negative differential signal terminals must be kept matched and as short as possible to the
TPB0 – 41 external load resistors and to the cable connector. Request the S800 1394b layout
TPB0+ 42 recommendations document from your Texas Instruments representative.
TPA1 – Cable 52 I/O Port-1 twisted-pair differential-signal terminals. Board traces from each pair of positive and
TPA1+ 53 negative differential signal terminals must be kept matched and as short as possible to the
TPB1 – 48 external load resistors and to the cable connector. Request the S800 1394b layout
TPB1+ 49 recommendations document from your Texas Instruments representative.
TPA2 – Cable 58 I/O Port-2 twisted-pair differential-signal terminals. Board traces from each pair of positive and
TPA2+ 59 negative differential signal terminals must be kept matched and as short as possible to the
TPB2 – 55 external load resistors and to the cable connector. Request the S800 1394b layout
TPB2+ 56 recommendations document from your Texas Instruments representative.
TPBIAS0_SD0 Cable In 47 I/O Twisted-pair bias output and signal detect input. This provides the 1.86-V nominal bias
TPBIAS1_SD1 54 voltage needed for proper operation of the twisted-pair cable drivers and receivers, and for
TPBIAS2_SD2 60 signaling to the remote nodes that there is an active cable connection in 1394a-2000 mode.
Each of these terminals, except for an unused port, must be decoupled with a 1- µ F
capacitor to ground. For the unused port, this terminal can be left unconnected.
When a port is configured as a Beta-mode port (B1, B2, B4) this terminal becomes an input
and must be high when a valid signal is present. For optical transceivers, the signal detect
of the transceiver must be connected to this terminal. The input is an LVCMOS level input.
VREG_PD CMOS 73 I Voltage regulator power-down input. When asserted logic-high, this terminal powers down
the internal 3.3-V-to-1.8-V regulator. For single-supply (3.3-V only) operation, this terminal
must be tied to GND.
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