Datasheet

3–14
Table 3–15. Mux Control Register Description (GPO1 Field)
GPO1 FIELD (BITS 20–23) DESCRIPTION of GPO1 PIN (PIN #49)
0 0 0 0 CYDNE
0 0 0 1 CYDNE
†
0 0 1 0 GRFEMP (synchronous to BCLK)
0 0 1 1 CYCLEOUT
†
0 1 0 0 ATF full (synchronous to BCLK)
0 1 0 1 ATF empty (synchronous to BCLK)
0 1 1 0 ITF full (synchronous to BCLK)
0 1 1 1 ITF empty (synchronous to BCLK)
1 0 0 0 ACKRCV
†
1 0 0 1 (SCLK/2)
1 0 1 0 ArbGp (synchronous to SCLK)
1 0 1 1 FrGp (synchronous to SCLK)
1 1 0 0 RxDta
†
1 1 0 1 Constant zero (drive low)
1 1 1 0 Constant zero (drive low)
1 1 1 1 Constant one (drive high)
†
Synchronous to (SCLK/2)