Datasheet

3–5
Table 3–3. Control-Register Field Descriptions (Continued)
BITS ACRONYM FUNCTION NAME DESCRIPTION
20 CyMas Cycle master When CyMas is set and the TSB12LV01B is attached to the root
phy, the cyclemaster function is enabled. When the cycle_count
field of the cycle timer register increments, the transmitter sends
a cycle-start packet. This bit is not cleared upon bus reset. If
another node is selected as root during a bus reset, the
transaction layer in the now non-root TSB12LV01B node must
clear this bit.
21 CySrc Cycle source When CySrc is set, the cycle_count field increments and the
cycle_offset field resets for each positive transition of CYCLEIN.
When CySrc is cleared, the cycle_count field increments when
the cycle_offset field rolls over.
22 CyTEn Cycle-timer enable When CyTEn is set, the cycle_offset field increments. This bit
must be set to transmit cycle-start packets if node is cycle master.
23 TrgEn Trigger size function
enable
If TrgEn is set, the receiver will partition the received packet into
trigger size blocks. Trigger size is defined in the FIFO Control
register. The purpose of the trigger size function is to allow the
receiver to receive a packet larger than the GRF size. The host
bus can read the received data when each block is available
without waiting for the whole packet to be loaded into the GRF.
Host bus latency is therefore reduced.
24 IRP1En IR port 1 enable When IRP1En is set, the receiver accepts isochronous packets
when the channel number matches the value in the IR Port1 field
@ address 18h.
25 IRP2En IR port 2 enable When IRP2En is set, the receiver accepts isochronous packets
when the channel number matches the value in the IR Port2 field
@ address 18h.
26 – 30 Reserved Reserved Reserved
31 FhBad Flush Bad Packets When FhBad is set, the receiver flushes any received bad
packets (including a partial packet due to a GRF full condition)
and does not generate a RxDta interrupt. Setting FhBad also
disables the TrgEn function.
3.2.4 Interrupt and Interrupt-Mask Registers (@0Ch, @10h)
The interrupt and interrupt-mask registers work in tandem to inform the host bus interface when the state
of the TSB12LV01B changes. The interrupt mask register is read/write. When regRW (in the diagnostics
register @20h) is cleared to 0, the interrupt register (except for the Int bit) is cleared. When regRW is set
to 1, the interrupt register (including the Int bit) is read/write.
The interrupt bits all work the same. For example, when a PHY interrupt occurs, the PhInt bit is set. If the
PhIntMask bit is set, the Int bit is set. If the IntMask is set, the INT signal is asserted. The logic for the interrupt
bits is shown in Figure 3–2. Table 3–4 defines the interrupt and interrupt-mask register field descriptions.
As shown in Figure 3–2, the INT bit is the OR of interrupt bits 1 – 31. When all the interrupt bits are cleared,
INT equals 0. When any of the interrupt bits are set, INT is set 1, even if the INT bit was just cleared.
To reset the interrupt register, the host controller needs to write back the last value read. For example, if
‘3A7B00CF’h was read from the interrupt register, in order to cause all bits to reset to 0, the host controller
must write a ‘3A7B00CF’h to the interrupt register.
The interrupt register initial value is 1000_0000h
The interrupt mask register initial value is 0000_0000h