Datasheet

PWRGD
VIN
PGND
PH
VOUT
RT/CLK
VADJ
STSEL
SS/TR
VSENSE+
TPS84210
PWRGD
Logic
+
+
VREF
Comp
Power
Stage
and
Control
Logic
Thermal Shutdown
Shutdown
Logic
VIN
UVLO
OSC w/PLL
INH/UVLO
AGNDOCP
TPS84210
www.ti.com SLUSAN7A –SEPTEMBER 2011–REVISED MARCH 2012
ELECTRICAL CHARACTERISTICS (continued)
Over -40°C to 85°C free-air temperature, VIN = 3.3 V, V
OUT
= 1.8 V, I
OUT
= 2A,
C
IN1
= 47 µF ceramic, C
IN2
= 220 µF poly-tantalum, C
OUT1
= 47 µF ceramic, C
OUT2
= 100 µF poly-tantalum (unless otherwise
noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Ceramic 47
(5)
C
IN
External input capacitance µF
Non-ceramic 220
(5)
Ceramic 47
(6)
150 650
(7)
µF
C
OUT
External output capacitance Non-ceramic 100
(6)
1000
(7)
Equivalent series resistance (ESR) 25 mΩ
(5) A minimum of 47µF of ceramic capacitance is required across the input for proper operation. Locate the capacitor close to the device.
An additional 220µF of bulk capacitance is recommended. See Table 5 for more details.
(6) The amount of required output capacitance varies depending on the output voltage (see Table 3 ). The amount of required capacitance
must include at least 47µF of ceramic capacitance. Locate the capacitance close to the device. Adding additional capacitance close to
the load improves the response of the regulator to load transients. See Table 3 and Table 5 for more details.
(7) When using both ceramic and non-ceramic output capacitance, the combined maximum must not exceed 1200µF.
DEVICE INFORMATION
FUNCTIONAL BLOCK DIAGRAM
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