Datasheet

TPS7A16
SBVS171D –DECEMBER 2011–REVISED JANUARY 2014 www.ti.com
Table 1. Selected Resistor Combinations
V
OUT
R
1
R
2
V
OUT
/(R
1
+ R
2
) « I
Q
NOMINAL ACCURACY
1.194 V 0 Ω ∞ 0 µA ±2%
1.8 V 1.18 MΩ 2.32 MΩ 514 nA ±(2% + 0.14%)
2..5 V 1.5 MΩ 1.37 MΩ 871 nA ±(2% + 0.16%)
3.3 V 2 MΩ 1.13 MΩ 1056 nA ±(2% + 0.35%)
5 V 3.4 MΩ 1.07 MΩ 1115 nA ±(2% + 0.39%)
10 V 7.87 MΩ 1.07 MΩ 1115 nA ±(2% + 0.42%)
12 V 14.3 MΩ 1.58 MΩ 755 nA ±(2% + 0.18%)
15 V 42.2 MΩ 3.65 MΩ 327 nA ±(2% + 0.19%)
18 V 16.2 MΩ 1.15 MΩ 1038 nA ±(2% + 0.26%)
Close attention must be paid to board contamination when using high-value resistors; board contaminants may
significantly impact voltage accuracy. If board cleaning measures cannot be ensured, consider using a fixed-
voltage version of the TPS7A16 or using resistors in the order of hundreds or tens of kΩ.
CAPACITOR RECOMMENDATIONS
Low equivalent series resistance (ESR) capacitors should be used for the input, output, and feed-forward
capacitors. Ceramic capacitors with X7R and X5R dielectrics are preferred. These dielectrics offer more stable
characteristics. Ceramic X7R capacitors offer improved over-temperature performance, while ceramic X5R
capacitors are the most cost-effective and are available in higher values.
Note that high ESR capacitors may degrade PSRR.
INPUT AND OUTPUT CAPACITOR REQUIREMENTS
The TPS7A16 family of ultra-low power, high-voltage linear regulators achieves stability with a minimum input
capacitance of 0.1 µF and output capacitance of 2.2 µF; however, it is recommended to use a 10-µF ceramic
capacitor to maximize ac performance.
POWER-GOOD
The power-good (PG) pin is an open-drain output and can be connected to any 5.5-V or lower rail through an
external pull-up resistor. When no C
DELAY
is used, the PG output is high-impedance when V
OUT
is greater than
the PG trip threshold (V
IT
). If V
OUT
drops below V
IT
, the open-drain output turns on and pulls the PG output low. If
output voltage monitoring is not needed, the PG pin can be left floating or connected to GND.
The power-good feature functionality is only guaranteed when V
IN
≥ 3V (V
IN_MIN
)
Power-Good Delay and Delay Capacitor
The power-good delay time (t
DELAY
) is defined as the time period from when V
OUT
exceeds the PG trip threshold
voltage (V
IT
) to when the PG output is high. This power-good delay time is set by an external capacitor (C
DELAY
)
connected from the DELAY pin to GND; this capacitor is charged from 0 V to ~1.8 V by the DELAY pin current
(I
DELAY
) once V
OUT
exceeds the PG trip threshold (V
IT
).
When C
DELAY
is used, the PG output is high-impedance when V
OUT
exceeds V
IT
, and V
DELAY
exceeds V
REF
.
The power-good delay time can be calculated using: t
DELAY
= (C
DELAY
× V
REF
)/I
DELAY
. For example, when C
DELAY
= 10 nF, the PG delay time is approximately 12ms; that is, (10 nF × 1.193 V)/1 µA = 11.93 ms.
FEED-FORWARD CAPACITOR
Although a feed-forward capacitor (C
FF
) from OUT to FB is not needed to achieve stability, it is recommended to
use a 0.01-µF feed-forward capacitor to maximize ac performance.
TRANSIENT RESPONSE
As with any regulator, increasing the size of the output capacitor reduces over/undershoot magnitude but
increases the duration of the transient response.
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