Datasheet

V
OUT
+ V
REF
ǒ
1)
R1
R2
Ǔ
GNDEN NR
IN OUT
V
IN
V
OUT
0.01
µ
F
TPS796xx
2.2µF 1 µF
TPS796
www.ti.com SLVS351O –SEPTEMBER 2002 –REVISED NOVEMBER 2013
APPLICATION INFORMATION
The TPS796xx family of low-dropout (LDO) regulators For example, the TPS79630 exhibits 40μV
RMS
of
has been optimized for use in noise-sensitive output voltage noise using a 0.1μF ceramic bypass
equipment. The device features extremely low capacitor and a 10μF ceramic output capacitor. Note
dropout voltages, high PSRR, ultralow output noise, that the output starts up slower as the bypass
low quiescent current (265μA typically), and enable capacitance increases due to the RC time constant at
input to reduce supply currents to less than 1μA the bypass pin that is created by the internal 250kΩ
when the regulator is turned off. resistor and external capacitor.
A typical application circuit is shown in Figure 22.
Board Layout Recommendation to Improve
PSRR and Noise Performance
To improve ac measurements like PSRR, output
noise, and transient response, it is recommended that
the board be designed with separate ground planes
for V
IN
and V
OUT
, with each ground plane connected
only at the ground pin of the device. In addition, the
Figure 22. Typical Application Circuit
ground connection for the bypass capacitor should
connect directly to the ground pin of the device.
External Capacitor Requirements
Regulator Mounting
Although not required, it is good analog design
The tab of the SOT223-6 package is electrically
practice to place a 0.1μF to 2.2μF capacitor near the
connected to ground. For best thermal performance,
input of the regulator to counteract reactive input
the tab of the surface-mount version should be
sources. A 2.2μF or larger ceramic input bypass
soldered directly to a circuit-board copper area.
capacitor, connected between IN and GND and
Increasing the copper area improves heat dissipation.
located close to the TPS796xx, is required for stability
and improves transient response, noise rejection, and
Solder pad footprint recommendations for the devices
ripple rejection. A higher-value input capacitor may be
are presented in an application bulletin Solder Pad
necessary if large, fast-rise-time load transients are
Recommendations for Surface-Mount Devices,
anticipated and the device is located several inches
literature number AB-132, available for download
from the power source.
from the TI web site (www.ti.com).
Like most low dropout regulators, the TPS796xx
Programming the TPS79601 Adjustable LDO
requires an output capacitor connected between OUT
Regulator
and GND to stabilize the internal control loop. The
minimum recommended capacitor is 1μF. Any 1μF or
The output voltage of the TPS79601 adjustable
larger ceramic capacitor is suitable.
regulator is programmed using an external resistor
divider (see Figure 23). The output voltage is
The internal voltage reference is a key source of
calculated using Equation 1:
noise in an LDO regulator. The TPS796xx has an NR
pin which is connected to the voltage reference
through a 250kΩ internal resistor. The 250kΩ internal
(1)
resistor, in conjunction with an external bypass
where:
capacitor connected to the NR pin, creates a low-
• V
REF
= 1.2246V typ (the internal reference
pass filter to reduce the voltage reference noise and,
voltage)
therefore, the noise at the regulator output. In order
for the regulator to operate properly, the current flow
Resistors R1 and R2 should be chosen for
out of the NR pin must be at a minimum, because
approximately 40μA divider current. Lower value
any leakage current creates an IR drop across the
resistors can be used for improved noise
internal resistor, thus creating an output error.
performance, but the device wastes more power.
Therefore, the bypass capacitor must have minimal
Higher values should be avoided, as leakage current
leakage current. The bypass capacitor should be no
at FB increases the output voltage error.
more than 0.1μF in order to ensure that it is fully
charged during the quickstart time provided by the
internal switch shown in the functional block diagram.
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