Datasheet
ABSOLUTE MAXIMUM RATINGS
DISSIPATION RATINGS
TPS775xx, TPS776xx
SLVS232J – SEPTEMBER 1999 – REVISED MARCH 2009 ..............................................................................................................................................
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This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION
(1)
PRODUCT V
OUT
(2)
TPS775 xxyyyz, TPS776 xxyyyz XX is nominal output voltage (for example, 28 = 2.8V, 285 = 2.85V, 01 = Adjustable).
YYY is package designator.
Z is package quantity.
(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com .
(2) Custom fixed output voltages are available; minimum order quantities may apply. Contact factory for details and availability.
Over operating temperature range (unless otherwise noted)
(1)
PARAMETER TPS775xx, TPS776xx UNIT
Input voltage range, V
IN
(2)
– 0.3 to +13.5 V
Voltage range at EN – 0.3 to +16.5 V
Maximum RESET voltage (TPS775xx) 16.5 V
Maximum PG voltage (TPS776xx) 16.5 V
Peak output current Internally limited
Voltage range at OUT, FB 7 V
Continuous total power dissipation See Dissipation Ratings Table
Operating junction temperature range, T
J
– 40 to +125 ° C
Storage junction temperature range , T
STG
– 65 to +150 ° C
ESD rating, HBM 2 kV
(1) Stresses above these ratings may cause permanent damage to the device. Exposure to absolute maximum conditions for extended
periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other
conditions beyond those specified is not implied.
(2) All voltages are with respect to network terminal ground.
AIRFLOW DERATING FACTOR
BOARD PACKAGE (CFM) T
A
< +25 ° C (mW) ABOVE T
A
= +25 ° C T
A
= +70 ° C (mW) T
A
= +85 ° C (mW)
0 568 5.68mW/ ° C 312 227
— D
250 904 9.04mW/ ° C 497 362
0 2350 23.5mW/ ° C 1300 940
Low-K
(1)
PWP
300 3460 34.6mW/ ° C 1900 1400
0 2380 23.8mW/ ° C 1300 952
High-K
(2)
PWP
300 5790 57.9mW/ ° C 3200 2300
(1) This parameter is measured with the recommended copper heat sink pattern on a 1-layer, 5in × 5in printed circuit board (PCB), 1-ounce
copper, 2in × 2in coverage (4in
2
).
(2) This parameter is measured with the recommended copper heat sink pattern on a 8-layer, 1.5in × 2in PCB, 1-ounce copper with layers
1, 2, 4, 5, 7, and 8 at 5% coverage (0.9in
2
) and layers 3 and 6 at 100% coverage (6in
2
). For more information, refer to TI technical brief
SLMA002 .
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