Datasheet

TPS77301/315/316/318/327/328/333/350 WITH RESET OUTPUT
TPS77401/415/418/427/428/433/450 WITH POWER GOOD OUTPUT
250-mA LDO REGULATORS WITH 8-PIN MSOP PACKAGING
SLVS281E – FEBRUARY 2000 – REVISED JULY 2001
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS774xx PG timing diagram
†
V
res
is the minimum input voltage for a valid PG. The symbol V
res
is not currently listed within EIA or JEDEC standards for semiconductor
symbology.
V
I
V
res
†
t
t
t
V
O
Threshold
Voltage
PG
Output
Output
Undefined
Output
Undefined
V
IT+
‡
V
IT–
‡
V
IT–
‡
V
IT+
‡
‡
V
IT
– Trip voltage is typically 18% lower than the output voltage (82%V
O
) V
IT–
to V
IT+
is the hysteresis voltage.
V
res
†