Datasheet

Line regulation (mV) +
ǒ
%ńV
Ǔ
V
O
ǒ
5.5 V * V
Imin
Ǔ
100
1000
TPS72501
TPS72515, TPS72516
TPS72518, TPS72525
www.ti.com SLVS341E –MAY 2002–REVISED JUNE 2010
PACKAGE DISSIPATION RATINGS
PACKAGE BOARD R
qJC
R
qJA
DDPAK High K
(1)
2 °C/W 23 °C/W
SOT223 Low K
(2)
15 °C/W 53 °C/W
D-8 High K
(1)
39.4 °C/W 55 °C/W
(1) The JEDEC high-K (2s2p) board design used to derive this data was a 3-inch x 3-inch (7.5-cm x 7.5-cm), multilayer board with 1 ounce
internal power and ground planes and 2 ounce copper traces on top and bottom of the board.
(2) The JEDEC low-K (1s) board design used to derive this data was a 3-inch x 3-inch (7.5-cm x 7.5-cm), two-layer board with 2 ounce
copper traces on top of the board.
ELECTRICAL CHARACTERISTICS
over recommended operating free-air temperature range V
I
= V
O(typ)
+ 1 V, I
O
= 1 mA, EN = IN, C
o
= 1 µF, C
i
= 1 µF (unless
otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Bandgap voltage reference 1.177 1.220 1.263 V
TPS72501
0 µA < I
O
< 1 A
(1)
1.22 V ≤ V
O
≤ 5.5 V 0.965 V
O
1.035 V
O
Adjustable
T
J
= 25°C 1.5
TPS72515
0 µA< I
O
< 1 A 1.8 V ≤ V
I
≤ 5.5 V 1.47 1.53
T
J
= 25°C 1.6
TPS72516
V
O
Output voltage V
0 µA < I
O
< 1 A 2.6 V ≤ V
I
≤ 5.5 V 1.568 1.632
T
J
= 25°C 1.8
TPS72518
0 µA < I
O
< 1 A 2.8 V ≤ V
I
≤ 5.5 V 1.764 1.836
T
J
= 25°C 2.5
TPS72525
0 µA < I
O
< 1 A 3.5 V ≤ V
I
≤ 5.5 V 2.45 2.55
I
O
= 0 µA 75 120
I Ground current µA
I
O
= 1 A 210 300
EN < 0.4 V T
J
= 25°C 0.2
Standby current µA
EN < 0.4 V 1
BW = 200 Hz to 100 kHz, C
o
= 10 µF, I
O
= 1
V
n
Output noise voltage 150 µV
T
J
= 25°C mA
PSRR Ripple rejection f = 1 kHz, C
o
= 10 µF T
J
= 25°C 60 dB
Current limit
(2)
1.1 1.6 2.3 A
Output voltage line regulation
V
O
+ 1 V < V
I
≤ 5.5 V -0.15 0.02 0.15 %/V
(ΔV
O
/V
O
)
(3)
Output voltage load regulation 0 µA < I
O
< 1 A -0.25 0.05 0.25 %/A
V
IH
EN high level input
(2)
1.3
V
V
IL
EN low level input
(2)
-0.2 0.4
I
I
EN input current EN = 0 V or V
I
0.01 100 nA
I
(FB)
Feedback current TPS72501 V
(FB)
= 1.22 -100 100 nA
UVLO threshold V
CC
rising 1.45 1.57 1.70 V
UVLO hysteresis T
J
= 25°C, V
CC
rising 50 mV
UVLO deglitch T
J
= 25°C, V
CC
rising 10 µs
UVLO delay T
J
= 25°C, V
CC
rising 100 µs
(1) Minimum IN operating voltage used for testing is V
O(typ)
+ 1 V.
(2) Test condition includes output voltage V
O
= V
O
- 15% and pulse duration = 10 ms.
(3) V
Imin
= (V
O
+ 1) or 1.8 V whichever is greater.
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