Datasheet

1.8 V
V
IN1
V
IN2
EN
SEQ
V
OUT1
V
SENSE1
PG1
MR2
RESET
MR1
V
SENSE2
V
OUT2
TPS70351PWP
5 V
3.3 V
I/O
MR1
Core
0.22 Fm
RESET
22 Fm
47 Fm
0.22 Fm
DSP
MR2
PG1
EN
250 kW
>2 V
<0.7 V
250 kW
83%
95%
120ms
EN
V
OUT2
(Core)
PG1
RESET
SEQ
95%
83%
V
OUT1
(I/O)
t
1
(see NoteA)
NOTEA:t :TimeatwhichbothV andV aregreaterthanthePGthresholdsand islogichigh.
1 OUT1 OUT2
MR1
TPS70345, TPS70348
TPS70351, TPS70358
TPS70302
SLVS285H –AUGUST 2000–REVISED APRIL 2010 www.ti.com
APPLICATION INFORMATION
Split Voltage DSP Application
Figure 43 shows a typical application where the TPS70351 is powering up a DSP. In this application, by
grounding the SEQ pin, V
OUT1
(I/O) powers up first, and then V
OUT2
(core).
Figure 43. Application Timing Diagram (SEQ = Low)
32 Submit Documentation Feedback Copyright © 2000–2010, Texas Instruments Incorporated