Datasheet

VBAT
DEVOFF(register)
NRESPWRON
REGEN
32K OUTCLK
DCDCs
LDOs
SYSEN
HFCLKOUT
CLKEN
NEXT_Startup_event
18 sm
1.2ms
1.2ms
1.2ms
18 sm
18 sm
18 sm
3.42msbeforedetectionofstartingevent
126 sm
032-013
TPS65950
SWCS032E–OCTOBER 2008–REVISED JANUARY 2011 www.ti.com
NOTE: All timings are typical values with the default setup (depending on the resynchronization between power domains,
state machinery priority, etc.).
Figure 4-12. Power-Off Sequence in Master Modes
If the value of the HF clock is not 19.2 MHz (with the values of the CFG_BOOT HFCLK_FREQ bit field set
accordingly), the delay between DEVOFF and NRESPWRON/CLK32KOUT/SYSEN/HFCLKOUT is divided
by two (approximately 9 μs). This is caused by the internal frequency used by power STM switching from
3 to 1.5 MHz if the HF clock value is 19.2 MHz.
The DEVOFF event is PWRON falling edge in slave mode and DEVOFF internal register write in master
mode.
64 Power Module Copyright © 2008–2011, Texas Instruments Incorporated
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