Datasheet

I2S.SYNC
I2S.CLK
I2S.DIN
I2S.DOUT
23
22 1
0 23
22
1
0 23
22 1
0 23
22 1
0
23
22
1
0
23
22 1
0 23
22 1
0 23
22 1
0
Channel1 Channel2 Channel3 Channel4
T1
T3 T3 T3 T3 T3 T3 T3 T3
T4 T4 T4 T4 T4 T4 T4 T4
T5 T5 T5 T5 T5 T5 T5 T5
T2 T2 T2 T2
T0 T1
8dummy
bits
8dummy
bits
8dummy
bits
8dummy
bits
8dummy
bits
8dummy
bits
037-030
TPS65930/TPS65920
SWCS037G–MAY 2008– REVISED APRIL 2011 www.ti.com
12.4.2 TDM Data Format
Table 12-7 and Table 12-8 assume testing over the recommended operating conditions (see Figure 12-4).
Figure 12-4. TDM Interface—TDM Master Mode
100 Timing Requirements and Switching Characteristics Copyright © 2008–2011, Texas Instruments Incorporated
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