Datasheet

TPS65910 , TPS65910A , TPS65910A3 , TPS659101
TPS659102 , TPS659103 , TPS659104 , TPS659105
TPS659106, TPS659107, TPS659108, TPS659109
SWCS046U –MARCH 2010–REVISED JUNE 2014 www.ti.com
6.3.2 Switch-On/-Off Sequences
The power sequence is the automated switching on of the device resources when an off-to-active
transition takes place.
The device supports three embedded power sequences selectable by the device BOOT pins.
BOOT0 BOOT1 Processor Supported
0 0 AM3517, AM3505
1 0 OMAP3 Family, AM3715/03, DM3730/25
0 1 EEPROM sequence
Details of the boot sequence timing are given in Section 5.22.1. EEPROM sequences can be used for
specific power up sequence for corresponding application processor. For details of EEPROM sequence
refer to the user guides on the product folder: http://focus.ti.com/docs/prod/folders/print/tps65910.html.
6.3.3 Control Signals
6.3.3.1 SLEEP
When none of the device sleep-disable conditions are met, a falling edge (default, or rising edge,
depending on the programmed polarity) of this signal causes an ACTIVE-to-SLEEP state transition of the
device. A rising edge (default, or falling edge, depending on the programmed polarity) causes a transition
back to ACTIVE state. This input signal is level sensitive and no debouncing is applied.
While the device is in SLEEP state, predefined resources are automatically set in their low-power mode or
off. Resources can be kept in their active mode: (full-load capability), programming the
SLEEP_KEEP_LDO_ON and the SLEEP_KEEP_RES_ON registers. These registers contain 1 bit per
power resource. If the bit is set to 1, then that resource stays in active mode when the device is in SLEEP
state. 32KCLKOUT is also included in the SLEEP_KEEP_RES_ON register and the 32-kHz clock output is
maintained in SLEEP state if the corresponding mask bit is set.
6.3.3.2 PWRHOLD
When none of the device power-on disable conditions are met, a rising edge of this signal causes an OFF-
to-ACTIVE state transition of the device and a falling edge causes a transition back to OFF state.
Typically, this signal is used to control the device in a slave configuration. It can be connected to the
SYSEN output signal from other TPS659xx devices, or the NRESPWRON signal of another TPS65910
device. This input signal is level sensitive and no debouncing is applied.
A rising edge of PWRHOLD is highlighted though an associated interrupt.
6.3.3.3 BOOT0/BOOT1
These signals determine which processor the device is working with and hence which power-up sequence
is needed. See Section 5.22.1 for more details. There is no debouncing on this input signal.
6.3.3.4 NRESPWRON
This signal is used as the reset to the processor. It is held low until the ACTIVE state is reached. See
Section 5.22.2 to get detailed timing.
6.3.3.5 CLK32KOUT
This signal is the output of the 32K oscillator, which can be enabled or not during the power-on sequence,
depending on the Boot mode. It can be enabled and disabled by register bit, during ACTIVE state of the
device. CLK32KOUT output can also be enabled or not during SLEEP state of the device depending on
the SLEEPMASK register programming.
48 Detailed Description Copyright © 2010–2014, Texas Instruments Incorporated
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Product Folder Links: TPS65910 TPS65910A TPS65910A3 TPS659101 TPS659102 TPS659103 TPS659104
TPS659105 TPS659106 TPS659107 TPS659108 TPS659109