Datasheet
SERIAL INTERFACE
Overview
Register Default Values
I
2
C Address
Incremental Read
I
2
C Bus Release
Sleep Mode Operation
I
2
C Bus Error Recovery
I
2
C Communication Protocol
TPS65820
SLVS663B – MAY 2006 – REVISED APRIL 2008 ..............................................................................................................................................................
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The TPS65820 is compatible with a host-controlled environment, with internal parameters and status information
accessible via an I
2
C interface. An I
2
C communication port provides a simple way for an I
2
C compatible host to
access system status information and reset fault modes, functioning as a SLAVE port enabling I
2
C compatible
hosts to WRITE to or to READ from internal registers. The TPS65820 I
2
C port is a 2-wire bidirectional interface
using SCL (clock) and SDA (data) pins; the SDA pin is open drain and requires an external pullup. The I
2
C is
designed to operate at SCL frequencies up to 400 kHz. The standard 8 bit command is supported, the CMD part
of the sequence is the 8 bit register address to READ from or to WRITE to.
The internal TPS65820 registers are loaded during the initial power-up from an internal, non-volatile memory
bank. The power-up default values are described in the sections detailing the registers functionality.
The register contents remain intact as long as OUT pin voltage remains above the internal UVLO threshold,
V
UVLO
When the OUT pin voltage falls below the VUVLO threshold all register bits are reset to the internal power
up default.
The I
2
C specification contains several global addresses, which the slaves on the bus are required to respond to.
The TPS65820 only responds (ACK) to addresses: 0x90 and 0x91 and does not respond (NACK) to any other
address.
Table 1. TPS65820 I
2
C Read/Write Address
BYTE BIT
MSB 6 5 4 3 2 1 LSB
TPS65820 I
2
C WRITE ADDRESS 1 0 0 1 0 0 0 0
TPS65820 I
2
C READ ADDRESS 1 0 0 1 0 0 0 1
I/O DATA BUS B7 B6 B5 B4 B3 B2 B1 B0
The TPS65820 does not support incremental read operations. Each register must be accessed in a single read
operation.
The TPS65820 I
2
C engine does not create START or STOP states on the I
2
C bus during normal operation.
When the sleep mode is set SDAT is held LO by the TPS65820. The overall system operation is not affected, as
in sleep mode all TPS65820 integrated supplies are disabled and no power is available for any external devices
connected to the TPS65820 SDAT pin. When sleep mode ends the SDAT pin is released before the TPS65820
integrated regulated supplies are enabled. See section on System Sequencing and TPS65820 Operating Modes
for additional details on sleep mode operation.
The I
2
C bus specification does not define a method to be used when recovering from a host side bus error.
During a read operation the SDA pin can be left in a LO state if the host has not sent enough SCL pulses to
complete a transaction (i.e., host side bus error). The TPS65820 clears any SDA LO condition if 10 SCL pulses
are sent by the host, enabling recovery from host side bus error events.
The following conventions are used when describing the communication protocol:
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