Datasheet

S A6 A5 A4 A3 A2 A1 A0 A S7 S6 S5 S4 S3 S2 S1 S0 A D7 D6 D5 D4 D3 D2 D1 D0 A P
S AStart Condition Acknowledge A6 A0... Device Address
R/nW
Read / not Write S7 S0... Sub-Address
D7 D0... Data
P Stop Condition
R/nW
Slave Address + R/nW Reg Address Data
TPS65217A, TPS65217B, TPS65217C, TPS65217D
www.ti.com SLVSB64F –NOVEMBER 2011–REVISED APRIL 2013
Table 5. Functional Differences Between Battery-Less/5-V Only Operation With and Without 20-V Input
Over-Voltage Protection (continued)
POWER SUPPLIED THROUGH AC PIN POWER SUPPLIED THROUGH BAT PIN
(CASE (1) AND (2)) (CASE (3))
Device enters OFF mode.
NOTE: If a battery is present in the system,
TPS65217 automatically switches from AC to
Response to input-over-voltage N/A.
BAT supply when AC input exceeds 6.5 V and
back to AC when AC input recovers to safe
operating voltage range.
I
2
C BUS OPERATION
The TPS65217 hosts a slave I
2
C interface that supports data rates up to 400 kbit/s and auto-increment
addressing and is compliant to I
2
C standard 3.0.
Figure 19. Sub-Address in I
2
C Transmission
The I
2
C Bus is a communications link between a controller and a series of slave terminals. The link is established
using a two-wired bus consisting of a serial clock signal (SCL) and a serial data signal (SDA). The serial clock is
sourced from the controller in all cases where the serial data line is bi-directional for data communication
between the controller and the slave terminals. Each device has an open Drain output to transmit data on the
serial data line. An external pull-up resistor must be placed on the serial data line to pull the drain output high
during data transmission.
Data transmission is initiated with a start bit from the controller as shown in Figure 21. The start condition is
recognized when the SDA line transitions from high to low during the high portion of the SCL signal. Upon
reception of a start bit, the device will receive serial data on the SDA input and check for valid address and
control information. If the appropriate group and address bits are set for the device, then the device will issue an
acknowledge pulse and prepare the receive of sub-address data. Sub-address data is decoded and responded
to as per the “Register Map” section of this document. Data transmission is completed by either the reception of
a stop condition or the reception of the data word sent to the device. A stop condition is recognized as a low to
high transition of the SDA input during the high portion of the SCL signal. All other transitions of the SDA line
must occur during the low portion of the SCL signal. An acknowledge is issued after the reception of valid
address, sub-address and data words. The I
2
C interfaces will auto-sequence through register addresses, so that
multiple data words can be sent for a given I
2
C transmission. Reference Figure 20 and Figure 21 for detail.
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Product Folder Links: TPS65217A TPS65217B TPS65217C TPS65217D