Datasheet

PRODUCTPREVIEW
S A6 A5 A4 A3 A2 A1 A0 A S7 S6 S5 S4 S3 S2 S1 S0 A D7 D6 D5 D4 D3 D2 D1 D0 A P
S AStart Condition Acknowledge A6 A0... Device Address
R/nW
Read / not Write
S7 S0... Sub-Address
D7 D0... Data
P Stop Condition
R/nW
Slave Address + R/nW Reg Address Data
TPS65186
www.ti.com SLVSB04 –JULY 2011
• When the temperature is equal or greater than the TMST_HOT[3:0] threshold, the TMST_HOT interrupt bit of
the INT1 register is set, and the nINT pin is pulled low.
• If the last temperature is different from the baseline temperature by ±2°C (default) or more, the DTX interrupt
bit of the INT1 register is set. The latest temperature becomes the new baseline temperature. Please note
that by default the DTX interrupt is disabled, i.e. the nINT pin is not pulled low unless the DTX_EN bit was
previously set high.
• If the last temperature change is less than ±2°C (default), no action is taken.
TYPICAL APPLICATION OF THE TEMPERATURE MONITOR
In a typical application the temperature monitor and interrupts are used in the following manner:
• After the WAKEUP pin has been pulled high, the Application Processor (AP) writes 0x80h to the TMST1
register (address 0x0Dh). This starts the temperature measurement.
• The AP waits for the EOC interrupt. Alternatively the AP can poll the CONV_END bit in register TMST1. This
will notify the AP that the A/D conversion is complete and the new temperature reading is available in the
TMST_VALUE register (address (0x00h).
• The AP reads the temperature value from the TMST_VALUE register (address (0x00h).
• If the temperature changes by ±2°C (default) or more from the first reading, the processor is notified by the
DTX interrupt. The A/P may or may not decide to select a different set of wave forms to drive the panel.
• If the temperature is outside the allowed operating range of the panel, the processor is notified by the THOT
and TCOLD interrupts, respectively. It may or may not decide to continue with the page update.
• Once an over/under temperature has been detected, the AP should reset the TMST_HOT_EN or
TMST_COLD_EN bits, respectively, to avoid the nINT pin to be continuously pulled low. The TMST_HOT and
TMST_COLD interrupt bits then should be polled continuously, to determine when the panel temperature
recovers to the normal operating range. Once the temperature has recovered, the TMST_HOT_EN or
TMST_COLD_EN bits should be set to ‘1’ again and normal operation can resume.
I
2
C BUS OPERATION
The TPS65186 hosts a slave I
2
C interface that supports data rates up to 400 kbit/s and auto-increment
addressing and is compliant to I
2
C standard 3.0.
Figure 28. Subaddress in I
2
C Transmission
The I
2
C Bus is a communications link between a controller and a series of slave terminals. The link is established
using a two-wire bus consisting of a serial clock signal (SCL) and a serial data signal (SDA). The serial clock is
sourced from the controller in all cases where the serial data line is bi-directional for data communication
between the controller and the slave terminals. Each device has an open drain output to transmit data on the
serial data line. An external pull-up resistor must be placed on the serial data line to pull the drain output high
during data transmission.
Data transmission is initiated with a start bit from the controller as shown in Figure 30. The start condition is
recognized when the SDA line transitions from high to low during the high portion of the SCL signal. Upon
reception of a start bit, the device will receive serial data on the SDA input and check for valid address and
control information. If the appropriate slave address bits are set for the device, then the device will issue an
acknowledge pulse and prepare to receive the register address. Depending on the R/nW bit, the next byte
received from the master is written to the addressed register (R/nW = 0) or the device responds with 8-bit data
from the register (R/nW = 1). Data transmission is completed by either the reception of a stop condition or the
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