Datasheet

www.ti.com
Enable and Power Sequencing (TPS65124)
SWN
TPS65124
D1
L1
C1
V
IN
= 3.3V
V
GL
C3
R4
R3
SWP
FBL
VMAIN
FBM
C5
R6
R5
V
MAIN
C4
BOOT
VGH
C2
V
GH
FBH
RUN
GATE
VIN
EN
V
LOGIC
= 3.3V
P1
PGND
AGND
A
A
ENVGH
ENVGL
ENVGH
ENVGL
EN
D2
optional
R1
R2
V
LOGIC
V
IN
RUN
GATE
V
MAIN
V
GL
V
GH
V
BOOT
5.75V
ENVGH
ENVGL
EN
Fault Protection
TPS65120, TPS65121, TPS65123, TPS65124
SLVS531A – JUNE 2004 – REVISED MARCH 2005
DETAILED DESCRIPTION (continued)
The TPS65124 controls the power sequencing of V
LOGIC
, V
MAIN
, V
GH
and V
GL
with four separate enable pins.
These pins must be terminated and not be left floating to prevent instability.
Once RUN is pulled high and the input voltage on VIN exceeds the rising input UVLO threshold, the reference is
turned on and the external P-channel MOSFET P1 (see Figure 20 ) is switched on by pulling GATE low. The
GATE is pulled down with a 100 k Ω resistor. The DC/DC converter then starts up, enabling the BOOT output.
Pulling enable pin high (EN) powers on the MAIN output. This power sequencing must occur before the gate
voltages are enabled. Conversely V
GL
and V
GH
output voltages must be turned off by pulling ENVGL and ENVGH
inputs to ground before the MAIN output is switch off.
To clamp the V
GL
output near zero when the MAIN output is still on, an external diode (D2) can be used. In some
applications this diode may already be implemented in the display.
Figure 20. Power Sequencing on Digital Supply Voltage, Figure 21. TPS65124 Programmable Power Sequence
V
LOGIC
All TPS6512x outputs are protected against a short circuit to ground. During steady-state operation, if the output
V
MAIN
, V
GH
or V
GL
falls below its fault detection threshold the device simultaneously turns off all three outputs.
Once V
MAIN
comes down to 700 mV typ, the GATE output is pulled to V
IN
, the auxiliary LDO (TPS65120/1/2) is
disabled and the device enters a shutdown state.
The auxiliary LDO present in TPS65120/1/2 has an integrated current foldback circuit for reliable short-circuit
protection.
The device can be enabled again by toggling the enable pins (RUN, EN) below 0.4 V or by cycling the input
voltage below the UVLO falling threshold (2.15 V typ).
16