Datasheet

Slave Address R/W A Register Address A
Data A P
S
1
7
1 1 1
1 1
8
8
A = Acknowledge
S = START condition
Sr = REPEATED START condition
P = STOP condition
From Master to TPS6235x
From TPS6235x to Master
“0” Write
Sr
1
Slave Address R/W
7
1
“1” Read
A
1
HS-MASTERCODE
R/W A REGISTER ADDRESS A DATA A/A P
”0” (write)
DataTransferred
(nxBytes+ Acknowledge)
S A Sr
SLAVE ADDRESS
HSModeContinues
F/SMode HSMode F/SMode
Sr Slave Address
Slave Address Byte
Register Address Byte
TPS62350, TPS62351
TPS62352, TPS62353
TPS62354, TPS62355, TPS62356
SLVS540E – MAY 2006 – REVISED APRIL 2008 .............................................................................................................................................................. www.ti.com
Figure 50. "Read" Data Transfer Format in F/S-Mode
Figure 51. Data Transfer Format in H/S-Mode
MSB LSB
X 1 0 0 1 0 A1 A0
The slave address byte is the first byte received following the START condition from the master device. The first
five bits (MSBs) of the address are factory preset to 10010. The next two bits (A1, A0) of the address are device
option dependent. For example, TPS62350 is factory preset to 00 and TPS62351 is preset to 10. Up to 4
TPS62350 type of devices can be connected to the same I
2
C-Bus. See the ordering information table for more
details.
MSB LSB
0 0 0 0 0 0 D1 D0
Following the successful acknowledgment of the slave address, the bus master sends a byte to the TPS6235x,
which contains the address of the register to be accessed. The TPS6235x contains four 8-bit registers accessible
via a bidirectional I
2
C-bus interface. All internal registers have read and write access.
Table 1. Register Description
Name Description
VSEL0 (read / write) 00
VSEL1 (read / write) 01
CONTROL1 (read / write) 10
CONTROL2 (read / write) 11
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Product Folder Link(s): TPS62350, TPS62351 TPS62352, TPS62353 TPS62354, TPS62355, TPS62356