Datasheet

Recognize START or
REPEATED START
Condition
Recognize STOP or
REPEATED START
Condition
Generate ACKNOWLEDGE
Signal
Acknowledgement
Signal From Slave
SDA
SCL
MSB
P
Sr
Sr
or
P
S
or
Sr
START or
Repeated START
Condition
STOP or
Repeated START
Condition
Clock Line Held Low While
Interrupts are Serviced
1 2 7 8 9
ACK
1 2 3 − 8 9
ACK
Address
R/W
TPS6235x I
2
C Update Sequence
Slave Address R/W A Register Address A Data A PS
1
7
1 1 1 1 1
8 8
A = Acknowledge
S = START condition
P = STOP condition
From Master to TPS6235x
From TPS6235x to Master
“0” Write
TPS62350, TPS62351
TPS62352, TPS62353
TPS62354, TPS62355, TPS62356
www.ti.com .............................................................................................................................................................. SLVS540E – MAY 2006 – REVISED APRIL 2008
Figure 48. Bus Protocol
The TPS6235x requires a start condition, a valid I
2
C address, a register address byte, and a data byte for a
single update. After the receipt of each byte, TPS6235x device acknowledges by pulling the SDA line low during
the high period of a single clock pulse. A valid I
2
C address selects the TPS6235x. TPS6235x performs an update
on the falling edge of the LSB byte.
When the TPS6235x is in hardware shutdown (EN pin tied to ground) the device can not be updated via the I
2
C
interface. Conversely, the I
2
C interface is fully functional during software shutdown (EN_DCDC bit=0).
Figure 49. "Write" Data Transfer Format in F/S-Mode
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Product Folder Link(s): TPS62350, TPS62351 TPS62352, TPS62353 TPS62354, TPS62355, TPS62356