Datasheet

÷
÷
ø
ö
ç
ç
è
æ
+×
×
=
21
11
252
1
RRpF
f
pole
p
pFR
f
zero
252
1
1
××
=
p
CL
f
LC
×
=
p2
1
TPS62170, TPS62171
TPS62172, TPS62173
www.ti.com SLVSAT8C –NOVEMBER 2011–REVISED SEPTEMBER 2013
NOTE
DC Bias effect: High capacitance ceramic capacitors have a DC Bias effect, which will
have a strong influence on the final effective capacitance. Therefore the right capacitor
value has to be chosen carefully. Package size and voltage rating in combination with
dielectric material are responsible for differences between the rated capacitor value and
the effective capacitance.
spacing
Output Filter And Loop Stability
The devices of the TPS6217X family are internally compensated to be stable with L-C filter combinations
corresponding to a corner frequency to be calculated with Equation 10:
(10)
Proven nominal values for inductance and ceramic capacitance are given in Table 1 and are recommended for
use. Different values may work, but care has to be taken on the loop stability which will be affected. More
information including a detailed L-C stability matrix can be found in SLVA463.
The TPS6217X devices, both fixed and adjustable versions, include an internal 25pF feedforward capacitor,
connected between the VOS and FB pins. This capacitor impacts the frequency behavior and sets a pole and
zero in the control loop with the resistors of the feedback divider, per Equation 11 and Equation 12:
(11)
(12)
Though the TPS6217X devices are stable without the pole and zero being in a particular location, adjusting their
location to the specific needs of the application can provide better performance in Power Save mode and/or
improved transient response. An external feedforward capacitor can also be added. A more detailed discussion
on the optimization for stability vs. transient response can be found in SLVA289 and SLVA466.
If using ceramic capacitors, the DC bias effect has to be considered. The DC bias effect results in a drop in
effective capacitance as the voltage across the capacitor increases (see DC Bias effect NOTE in Capacitor
selection section).
Layout Considerations
A proper layout is critical for the operation of a switched mode power supply, even more at high switching
frequencies. Therefore the PCB layout of the TPS6217X demands careful attention to ensure operation and to
get the performance specified. A poor layout can lead to issues like poor regulation (both line and load), stability
and accuracy weaknesses, increased EMI radiation and noise sensitivity.
Provide low inductive and resistive paths to ground for loops with high di/dt. Therefore paths conducting the
switched load current should be as short and wide as possible. Provide low capacitive paths (with respect to all
other nodes) for wires with high dv/dt. Therefore the input and output capacitance should be placed as close as
possible to the IC pins and parallel wiring over long distances as well as narrow traces should be avoided. Loops
which conduct an alternating current should outline an area as small as possible, as this area is proportional to
the energy radiated.
Also sensitive nodes like FB and VOS should be connected with short wires, not nearby high dv/dt signals (e.g.
SW). As they carry information about the output voltage, they should be connected as close as possible to the
actual output voltage (at the output capacitor). Signals not assigned to power transmission (e.g. feedback divider)
should refer to the signal ground (AGND) and always be separated from the power ground (PGND).
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Product Folder Links: TPS62170 TPS62171 TPS62172 TPS62173