Datasheet

TPS61170
SLVS789C – NOVEMBER 2007– REVISED APRIL 2011 www.ti.com
The bit detection is based on a Logic Detection scheme, where the criterion is the relation between t
LOW
and
t
HIGH
. It can be simplified to:
High Bit: t
HIGH
> t
LOW
, but with t
HIGH
at least 2x t
LOW
, see Figure 16.
Low Bit: t
HIGH
< t
LOW
, but with t
LOW
at least 2x t
HIGH
, see Figure 16.
The bit detection starts with a falling edge on the CTRL pin and ends with the next falling edge. Depending on
the relation between t
HIGH
and t
LOW
, the logic 0 or 1 is detected.
The acknowledge condition is only applied if:
• Acknowledge is requested by a set RFA bit.
• The transmitted device address matches with the device address of the device.
• 16 bits is received correctly.
If the device turns on the internal ACKN-MOSFET and pulls the CTRL pin low for the time t
ACKN
, which is 512μs
maximum then the Acknowledge condition is valid after an internal delay time t
valACK
. This means that the internal
ACKN-MOSFET is turned on after t
valACK
, when the last falling edge of the protocol was detected. The master
controller keeps the line low in this period. The master device can detect the acknowledge condition with its input
by releasing the CTRL pin after t
valACK
and read back a logic 0. The CTRL pin can be used again after the
acknowledge condition ends.
Note that the acknowledge condition may only be requested if the master device has an open drain output. For
the push-pull output stage, the use a series resistor in the CRTL line to limit the current to 500μA is
recommended for such cases as:
• an accidentally requested acknowledge, or
• to protect the internal ACKN-MOSFET.
14 Copyright © 2007–2011, Texas Instruments Incorporated