Datasheet

TPS60200, TPS60201, TPS60202, TPS60203

REGULATED 3.3 V, 100-mA LOW-RIPPLE CHARGE PUMP

LOW POWER DC/DC CONVERTERS

SLVS274 – MARCH 2000

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

APPLICATION INFORMATION

power dissipation (continued)

DISS

must be less than that allowed by the package rating. The thermal resistance junction to ambient of the

used 10-pin MSOP is 294°C/W for an unsoldered package. The thermal resistance junction to ambient with

the IC soldered to a printed circuit using a board layout as described in the application information section, the

ΘJA

is typically 200°C/W, which is higher than the maximum value calculated above. However in a battery

powered application, both V

and T

will typically be lower than the worst case ratings used in equation 6 , and

power dissipation should not be a problem in most applications.

layout and board space

Careful board layout is necessary due to the high transient currents and switching frequency of the converter.

All capacitors should be placed in close proximity to the device. A PCB layout proposal for a one-layer board

is given in Figure 20.

An evaluation module for the TPS60200 is available and can be ordered under product code

TPS60200EVM–145. The EVM uses the layout shown in Figure 20. All components including the pins are

shown. The EVM is built so that it can be connected to a 14-pin dual inline socket, therefore, the space needed

for the IC, the external parts, and 8 pins is 17,9 mm x 10,2 mm = 182,6 mm

Figure 20. Recommended Component Placement and Board Layout

Table 5. Component Identification

IC1 TPS60200

C1, C2 Flying capacitors

C3 Input capacitors

C4 Output capacitors

C5 Stabilization capacitor for LBI

R1, R2 Resistive divider for LBI

R3 Pullup resistor for LBO

R4 Pullup resistor for EN

Capacitor C5 should be included if large line transients are expected. This capacitor suppresses toggling of the

LBO due to these line changes.