Datasheet

D
ICin _ rms = ILpri _ pospk ×
3
SEC
OUT
PRI
IN
SW CIN
N
I × D
N
C =
× VDf
TPS55010
www.ti.com SLVSAV0A –APRIL 2011–REVISED JUNE 2011
The input capacitance is calculated 12.6 µF using Equation 32 and the rms current is 0.46 A. A 47 µF/10V X5R
ceramic capacitor is used on the input. A 0.1 µF ceramic capacitor is placed as close to the VIN and GND pins
as possible for a good bias supply.
(32)
Spacer
(33)
Y – Capacitor
The Y-capacitor should be used between the primary and secondary to attenuate common mode (CM) noise in
noise sensitive applications. When connecting the primary and secondary grounds with a large loop area, the
primary side switching noise can be injected via the interwinding capacitance of the isolation transformer,
creating common mode noise in the secondary. A Y-capacitor can be used to provide a local return path for
these currents with a small capacitor connected between the secondary ground and the primary ground. The
voltage rating of the Y-capacitor should be equivalent to the transformer insulation voltage. If the converter is
used for safety isolation there is an upper limit on the amount of capacitance. The inter-winding capacitances of
the transformer and maximum leakage current (e.g. UL60950 Class I equipment leakage current <3.5 mA)
allowed by the safety standard will set the maximum value. It is not recommended to use the Y-capacitor in
applications which experience large voltage transients such as a floating gate drive supply in a power inverter.
SLOW START CAPACITOR
To minimize overshoot during power up or recovery from an overload condition a slow start capacitor is used. A
35-ms slow start is desired and using Equation 5 a 0.1 µF capacitor is calculated.
BOOTSTRAP CAPACITOR SELECTION
A 0.1 µF ceramic capacitor must be connected between the BOOT to PH pin for proper operation. It is
recommended to use a ceramic capacitor with X5R or better grade dielectric. The capacitor should have 10 V or
higher voltage rating.
UVLO Resistors
Using the start and stop voltages of 4.5 V and 4 V, respectively, the uvlo resistors 71.5 kΩ and 26.7 kΩ are
calculated using Equation 3 and Equation 4.
COMPENSATION
There are several methods used to compensate DC/DC regulators. The method presented here ignores the
effects of the slope compensation that is internal to the device. Since the slope compensation is ignored, the
actual cross over frequency should be lower than the cross over frequency used in the calculations. This method
assumes the cross over frequency is between the modulator pole and 20 times greater the modulator pole. When
choosing a crossover frequency with the single compensation capacitor method (i.e. type 1), use the lower end of
the recommended range when developing a supply if the primary capacitor ripple voltage is <1%. Type 2 or 3
compensation should be considered if a low primary ripple design is preferred. To get started, the modulator pole
frequency, f
POLE
, determined from Equation 10 should be used to select the crossover frequency, f
CO
. In this
example, 5 kHz is selected as the crossover frequency. The next step is to determine the compensation gain,
A
COMP
, at the crossover frequency to compensate the loop. Equation 35 uses the dc gain of the power stage,
modulator pole, and crossover frequency to estimate the gain. R
i
is the current sense gain which is the inverse of
the Comp to IPH transconductance, which is 7.5 A/V. 10.1 dB is calculated for A
COMP
. The compensation pole
frequency f
COMP_POLE
can be calculated using Equation 36. A
OL
in Equation 36 is the open loop gain of the error
amplifier and is 500 V/V. f
COMP_POLE
is calculated as 8.27 Hz. Using Equation 37, C
COMP
is calculated to be 0.01
μF.
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