Datasheet

Layout
3-2
3.1 Layout
The board layout for the TPS54x72EVM−222 is shown in Figure 3−1 through
Figure 3−6. The top side layer of the TPS54x72EVM−222 is laid out in a
manner typical of a user application. The bottom layer of the
TPS54x72EVM−222 is designed to accommodate an optional alternate output
filter configuration. The top and bottom layers are 1.5 oz. copper, while the two
internal layers are 0.5 oz. copper.
The top layer contains the main power traces for V
I
, V
O
, and V
(phase)
. Also on
the top layer are connections for the remaining pins of the TPS54x72 and a
large area filled with ground. The two internal layers are identical and are
dedicated ground planes. The bottom layer contains pads for an optional
alternate output filter including space for three D3 or D4 case size electrolytic
capacitors and an alternate inductor of 0.5 in. x 0.5 in. size ground traces. The
top and bottom ground traces are connected to the internal ground planes with
45 vias placed around the board including 12 directly under the TPS54x72
device to provide a thermal path from the PowerPAD land to ground.
The input-decoupling capacitors (C4 and C8), bias-decoupling capacitor (C9),
and boot-strap capacitor (C6) are all located as close to the IC as possible. In
addition, the compensation components are also kept close to the IC. The
compensation circuit ties to the output voltage at the point of regulation,
adjacent to the high frequency bypass output capacitor.
Figure 3−1. Top-Side Layout