Datasheet

RT/CLK
GND
PVIN
VIN
VSENSE
COMP
SS/TR
EN
PH
BOOT
PWRGD
GND
PVIN
PH
PH
EXPOSED THERMAL
PAD AREA
COMPENSATION
NETWORK
BOOT
CAPACITOR
PVIN
INPUT
BYPASS
CAPACITOR
VOUT
TOPSIDE
GROUND
AREA
VIA toGroundPlane
OUTPUT
INDUCTOR
OUTPUT
FILTER
CAPACITOR
FREQUENCY SET RESISTOR
SLOWSTART
CAPACITOR
ANALOGGROUND TRACE
VIN
INPUT
BYPASS
CAPACITOR
VIN
PVIN
UVLOSET
RESISTORS
FEEDBACK
RESISTORS
EtchUnderComponent
0.010in.Diameter
ThermalVIA toGroundPlane
TPS54620
SLVS949C – MAY 2009– REVISED MAY 2011 www.ti.com
adequate width. The small signal components should be grounded to the analog ground path as shown. The
RT/CLK pin is sensitive to noise so the RT resistor should be located as close as possible to the IC and routed
with minimal lengths of trace. The additional external components can be placed approximately as shown. It may
be possible to obtain acceptable performance with alternate PCB layouts, however this layout has been shown to
produce good results and is meant as a guideline.
Land pattern and stencil information is provided in the data sheet addendum. The dimension and outline
information is for the standard RHL (S-PVQFN-N14) package. There may be slight differences between the
provided data and actual lead frame used on the TPS54620RHL package.
Figure 56. PCB Layout
30 Copyright © 2009–2011, Texas Instruments Incorporated