Datasheet

TPS54618
www.ti.com SLVSAE9D –NOVEMBER 2010–REVISED DECEMBER 2013
Thermal Information
TPS54618
THERMAL METRIC
(1)
RTE UNITS
16 PINS
θ
JA
Junction-to-ambient thermal resistance
(2)
44.38
θ
JCtop
Junction-to-case (top) thermal resistance
(3)
46.09
θ
JB
Junction-to-board thermal resistance
(4)
15.96
°C/W
ψ
JT
Junction-to-top characterization parameter
(5)
0.69
ψ
JB
Junction-to-board characterization parameter
(6)
15.91
θ
JCbot
Junction-to-case (bottom) thermal resistance
(7)
4.55
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-
standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(5) The junction-to-top characterization parameter, ψ
JT
, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θ
JA
, using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-board characterization parameter, ψ
JB
, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θ
JA
, using a procedure described in JESD51-2a (sections 6 and 7).
(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
Spacer
ELECTRICAL CHARACTERISTICS
T
J
= –40°C to 150°C, VIN = 2.95 to 6 V (unless otherwise noted)
DESCRIPTION CONDITIONS MIN TYP MAX UNIT
SUPPLY VOLTAGE (VIN PIN)
Operating input voltage 2.95 6.0 V
VIN UVLO STOP 2.28 2.5
Internal under voltage lockout threshold V
VIN UVLO START 2.45 2.6
Shutdown supply current EN = 0 V, 25°C, 2.95 V ≤ VIN ≤ 6 V 5.5 15 μA
Quiescent current - I
q
VSENSE = 0.9 V, VIN = 5 V, 25°C, RT = 400 kΩ 515 650 μA
ENABLE AND UVLO (EN PIN)
Rising 1.25
Enable threshold V
Falling 1.18
Enable threshold + 50 mV –3.5
Input current μA
Enable threshold – 50 mV –1.9
VOLTAGE REFERENCE (VSENSE PIN)
Voltage Reference 2.95 V ≤ VIN ≤ 6 V, –40°C <T
J
< 150°C 0.791 0.799 0.807 V
MOSFET
BOOT-PH = 5 V 12 25
High side switch resistance mΩ
BOOT-PH = 2.95 V 16 33
VIN = 5 V 13 25
Low side switch resistance mΩ
VIN = 2.95 V 17 33
ERROR AMPLIFIER
Input current 2 nA
Error amplifier transconductance (gm) –2 μA < I
(COMP)
< 2 μA, V
(COMP
) = 1 V 245 μmhos
Error amplifier transconductance (gm) during –2 μA < I
(COMP)
< 2 μA, V
(COMP)
= 1 V,
79 μmhos
slow start Vsense = 0.4 V
Error amplifier source/sink V
(COMP)
= 1 V, 100 mV overdrive ±20 μA
COMP to Iswitch gm 25 A/V
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