Datasheet

Error Amplifier
PWM Control
Dead-Time Control and MOSFET Drivers
Overcurrent Protection
TPS54617
www.ti.com ........................................................................................................................................... SLVS880A – NOVEMBER 2008 – REVISED JANUARY 2009
Table 1. Summary of the Frequency Selection Configurations
SWITCHING FREQUENCY SYNC PIN RT PIN
350 kHz, internally set Float or AGND Float
550 kHz, internally set ≥ 2.5 V Float
Externally set 280 kHz to 1.6MHz Float R = 27 k to 180 k
Externally synchronized frequency Synchronization signal R = RT value for 80% of external synchronization frequency
low-side FET remains on until the VSENSE voltage
decreases to a range that allows the PWM
comparator to change states. The TPS54617 is
The high performance, wide bandwidth, voltage error
capable of sinking current continuously until the
amplifier sets the TPS54617 apart from most dc/dc
output reaches the regulation set-point.
converters. The user is given the flexibility to use a
wide range of output L and C filter components to suit
If the current limit comparator trips for longer than
the particular application needs. Type-2 or Type-3
100 ns, the PWM latch resets before the PWM ramp
compensation can be employed using external
exceeds the error amplifier output. The high-side FET
compensation components.
turns off and low-side FET turns on to decrease the
energy in the output inductor and consequently the
output current. This process is repeated each cycle in
which the current limit comparator is tripped.
Signals from the error amplifier output, oscillator, and
current limit circuit are processed by the PWM control
logic. Referring to the internal block diagram, the
control logic includes the PWM comparator, OR gate,
Adaptive dead-time control prevents shoot-through
PWM latch, and portions of the adaptive dead-time
current from flowing in both N-channel power
and control-logic block. During steady-state operation
MOSFETs during the switching transitions by actively
below the current limit threshold, the PWM
controlling the turnon times of the MOSFET drivers.
comparator output and oscillator pulse train
The high-side driver does not turn on until the voltage
alternately reset and set the PWM latch. Once the
at the gate of the low-side FET is below 2 V. While
PWM latch is set, the low-side FET remains on for a
the low-side driver does not turn on until the voltage
minimum duration set by the oscillator pulse width.
at the gate of the high-side MOSFET is below 2 V.
During this period, the PWM ramp discharges rapidly
The high-side and low-side drivers are designed with
to its valley voltage. When the ramp begins to charge
300-mA source and sink capability to drive the power
back up, the low-side FET turns off and high-side
MOSFETs gates. The low-side driver is supplied from
FET turns on. As the PWM ramp voltage exceeds the
VIN, while the high-side drive is supplied from the
error amplifier output voltage, the PWM comparator
BOOT pin. A bootstrap circuit uses an external BOOT
resets the latch, thus turning off the high-side FET
capacitor and an internal 2.5- Ω bootstrap switch
and turning on the low-side FET. The low-side FET
connected between the VIN and BOOT pins. The
remains on until the next oscillator pulse discharges
integrated bootstrap switch improves drive efficiency
the PWM ramp.
and reduces external component count.
During transient conditions, the error amplifier output
could be below the PWM ramp valley voltage or
above the PWM peak voltage. If the error amplifier is
The cycle-by-cycle current limiting is achieved by
high, the PWM latch is never reset, and the high-side
sensing the current flowing through the high-side
FET remains on until the oscillator pulse signals the
MOSFET and comparing this signal to a preset
control logic to turn the high-side FET off and the
overcurrent threshold. The high side MOSFET is
low-side FET on. The device operates at its
turned off within 200 ns of reaching the current limit
maximum duty cycle until the output voltage rises to
threshold. A 100-ns leading edge blanking circuit
the regulation set-point, setting VSENSE to
prevents current limit false tripping. Current limit
approximately the same voltage as VREF. If the error
detection occurs only when current flows from VIN to
amplifier output is low, the PWM latch is continually
PH when sourcing current to the output filter. Load
reset and the high-side FET does not turn on. The
protection during current sink operation is provided by
thermal shutdown.
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