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 

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SLVS519A − MAY 2004 − REVISED OCTOBER 2004

       

    

 !! y  !!

FEATURES

D 100 mΩ, 4.5-A Peak MOSFET Switch for High

Efficiency at 3-A Continuous Output Current

D Uses External Lowside MOSFET or Diode

D Fixed Output Versions −

1.2V/1.5V/1.8V/2.5V/3.3V/5.0V

D Internally Compensated for Low Parts Count

D Synchronizes to External Clock

D 1805 Out of Phase Synchronization

D Wide PWM Frequency − Fixed 250 kHz,

500 kHz or Adjustable 250 kHz to 700 kHz

D Internal Slow Start

D Load Protected by Peak Current Limit and

Thermal Shutdown

D Adjustable Undervoltage Lockout

D 16-Pin TSSOP PowerPADE Package

APPLICATIONS

D Industrial & Commercial Low Power Systems

D LCD Monitors and TVs

D Computer Peripherals

D Point of Load Regulation for High

Performance DSPs, FPGAs, ASICs and

Microprocessors

VIN

PGND

BOOT

VSENSE

PWRPAD

BIAS

ENA

PWRGD

Input

Voltage

Output

Voltage

LSG

TPS54356

SYNC

SIMPLIFIED SCHEMATIC

DESCRIPTION

The TPS5435x is a medium output current synchronous

buck PWM converter with an integrated high side

MOSFET and a gate driver for an optional low side

external MOSFET. Features include a high performance

voltage error amplifier that enables maximum

performance under transient conditions. The TPS5435x

has an under-voltage-lockout circuit to prevent start-up

until the input voltage reaches a preset value; an internal

slow-start circuit to limit in-rush currents; and a power good

output to indicate valid output conditions. The

synchronization feature is configurable as either an input

or an output for easy 180° out of phase synchronization.

The TPS5435x devices are available in a thermally

enhanced 16-pin TSSOP (PWP) PowerPAD package.

TI provides evaluation modules and the SWIFT Designer

software tool to aid in quickly achieving high-performance

power supply designs to meet aggressive equipment

development cycles.

100

01234

= 12 V

= 3.3 V

= 500 kHz

= 12 V

= 6 V

− Output Current − A

Efficiency − %

EFFICIENCY

OUTPUT CURRENT

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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments

semiconductor products and disclaimers thereto appears at the end of this data sheet.

www.ti.com

PowerPAD and SWIFT are trademarks of Texas Instruments.

Summary of content (37 pages)

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!! y !! www.ti.com SLVS519A − MAY 2004 − REVISED OCTOBER 2004  FEATURES D 100 mΩ, 4.5-A Peak MOSFET Switch for High D D D D D D D D D D Efficiency at 3-A Continuous Output Current Uses External Lowside MOSFET or Diode Fixed Output Versions − 1.2V/1.5V/1.8V/2.5V/3.3V/5.
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www.ti.com SLVS519A − MAY 2004 − REVISED OCTOBER 2004 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ORDERING INFORMATION TA −40°C to 85°C OUTPUT VOLTAGE PACKAGE PART NUMBER 1.2 V Plastic HTSSOP (PWP) TPS54352PWP 1.5 V Plastic HTSSOP (PWP) TPS54353PWP 1.
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www.ti.com SLVS519A − MAY 2004 − REVISED OCTOBER 2004 ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted(1) UNIT Input voltage range, VI Output voltage range, VO Source current, IO Sink current, IS Voltage differential VIN −0.3 V to 21.5 V VSENSE −0.3 V to 8.0 V UVLO −0.3 V to 8.0 V SYNC −0.3 V to 4.0 V ENA −0.3 V to 4.0 V BOOT VI(PH) + 8.0 V VBIAS −0.3 to 8.5 V LSG −0.3 to 8.5 V SYNC −0.
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www.ti.com SLVS519A − MAY 2004 − REVISED OCTOBER 2004 ELECTRICAL CHARACTERISTICS TJ = –40°C to 125°C, VIN = 4.5 V to 20 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY CURRENT IQ Operating current, PH pin open, No external low side MOSFET, RT = Hi-Z Quiescent current 5 Shutdown, ENA = 0 V 1 TPS54352−6 Start threshold voltage VIN Stop threshold voltage Hysteresis mA TPS54357 mA 4.32 4.49 6.4 6.
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www.ti.com SLVS519A − MAY 2004 − REVISED OCTOBER 2004 ELECTRICAL CHARACTERISTICS (CONTINUED) TJ = –40°C to 125°C, VIN = 4.
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www.ti.com SLVS519A − MAY 2004 − REVISED OCTOBER 2004 ELECTRICAL CHARACTERISTICS (CONTINUED) TJ = –40°C to 125°C, VIN = 4.5 V to 20 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT CURRENT LIMIT Current limit VIN = 12 V Current limit hiccup time (1) fs = 500 kHz 3.3 4.5 6.5 A 4.5 ms 165 _C 7 _C VIN = 4.5 V, Capacitive load = 1000 pF 15 ns VIN = 12 V 60 ns VIN = 4.5 V sink/source 7.
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www.ti.com SLVS519A − MAY 2004 − REVISED OCTOBER 2004 PIN ASSIGNMENTS PWP PACKAGE (TOP VIEW) VIN VIN UVLO PWRGD RT SYNC ENA COMP 1 2 3 4 5 6 7 8 THERMAL PAD 16 15 14 13 12 11 10 9 BOOT PH PH LSG VBIAS PGND AGND VSENSE NOTE: If there is not a Pin 1 indicator, turn device to enable reading the symbol from left to right. Pin 1 is at the lower left corner of the device. Terminal Functions TERMINAL NO.
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www.ti.com SLVS519A − MAY 2004 − REVISED OCTOBER 2004 FUNCTIONAL BLOCK DIAGRAM BOOT VIN PH 320 kΩ Hiccup UVLO UVLO 125 kΩ(1) SYNC Current Limit 1.
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www.ti.com SLVS519A − MAY 2004 − REVISED OCTOBER 2004 Input Voltage Supply 320 kΩ R1 R2 1 kΩ 125 kΩ (1) 5 µA Disabled (1) 75 kΩ for the TPS54357 RSS CSS Enabled Figure 1. Circuit Using External UVLO Function Figure 2. Interfacing to the ENA Pin For applications which require an undervoltage lock out (UVLO) threshold greater than 4.49 V (6.
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www.ti.com SLVS519A − MAY 2004 − REVISED OCTOBER 2004 Table 3. SWITCHING FREQUENCY SYNC PIN RT PIN 250 kHz, internally set Generates SYNC output signal AGND 500 kHz, internally set Generates SYNC output signal Float Externally set to 250 kHz to 700 kHz Terminate to quiet ground with 10-kΩ resistor. R = 215 kΩ to 69 kΩ Synchronization Signal Set RT resistor equal to 90% to 110% of external synchronization frequency.
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www.ti.com SLVS519A − MAY 2004 − REVISED OCTOBER 2004 Internal Oscillator VO(PH) VO(SYNC) Figure 4. SYNC Output Waveform Power Good (PWRGD) The VSENSE pin is compared to an internal reference signal, if the VSENSE is greater than 97% and no other faults are present, the PWRGD pin presents a high impedance. A low on the PWRGD pin indicates a fault.
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www.ti.com SLVS519A − MAY 2004 − REVISED OCTOBER 2004 Once the PWM latch is reset, the low-side driver and integrated pull-down MOSFET remain on for a minimum duration set by the oscillator pulse width. During this period, the PWM ramp discharges rapidly to the valley voltage. When the ramp begins to charge back up, the low-side driver turns off and the high-side FET turns on.
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www.ti.com SLVS519A − MAY 2004 − REVISED OCTOBER 2004 Switching Frequency Limitations Due to the internal design of the TPS54352−6 there are limitations to the maximum usable switching frequency for any given input voltage. This limit is constrained by the minimum controllable on time which may be as high as 220 ns. Figure 31 shows the maximum switching frequency versus input voltage for each device.
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www.ti.com SLVS519A − MAY 2004 − REVISED OCTOBER 2004 TYPICAL CHARACTERISTICS Conditions are VI = 12 V, VO = 3.3 V, fs = 500 kHz, IO = 3 A, TA = 25 °C, unless otherwise noted MEASURED LOOP RESPONSE 0.1 90 20 60 30 Gain 0 0 −10 −30 −20 −60 −30 −90 −40 −50 −60 100 Phase − Degrees 30 10 0.08 120 Phase −120 See Figure 25 1k 10 k 100 k −150 −180 1M 0.2 VI = 12 V 0.1 VI = 6 V 0 VI = 18 V −0.1 −0.2 −0.3 0 0.5 1 0.06 0 −0.
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www.ti.com SLVS519A − MAY 2004 − REVISED OCTOBER 2004 Conditions are VI = 12 V, VO = 3.
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www.ti.com SLVS519A − MAY 2004 − REVISED OCTOBER 2004 LAYOUT INFORMATION Figure 23. TPS5435x PCB Layout PCB LAYOUT The VIN pins should be connected together on the printed circuit board (PCB) and bypassed with a low ESR ceramic bypass capacitor. Care should be taken to minimize the loop area formed by the bypass capacitor connections, the VIN pins, and the TPS5435x ground pins.
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www.ti.com SLVS519A − MAY 2004 − REVISED OCTOBER 2004 j0.0130 8 PL Minimum recommended exposed copper area for powerpad. 5mil stencils may require 10 percent larger area. Minimum recommended thermal vias: 4 x .013 dia. inside powerpad area and 4 x .013 dia. under device as shown. Additional .018 dia. vias may be used if top side Analog Ground area is extended. 0.0150 0.06 0.0371 0.0400 0.1970 0.1942 0.0570 0.0400 0.0400 0.
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www.ti.com SLVS519A − MAY 2004 − REVISED OCTOBER 2004 APPLICATION INFORMATION + + Figure 25. Application Circuit, 12 V to 3.3 V Figure 25 shows the schematic for a typical TPS54356 application. The TPS54356 can provide up to 3-A output current at a nominal output voltage of 3.3 V. For proper thermal performance, the exposed PowerPAD underneath the device must be soldered down to the printed circuit board.
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www.ti.com SLVS519A − MAY 2004 − REVISED OCTOBER 2004 INPUT CAPACITORS The TPS54356 requires an input decoupling capacitor and, depending on the application, a bulk input capacitor. The minimum value for the decoupling capacitor, C9, is 10µF. A high quality ceramic type X5R or X7R is recommended. The voltage rating should be greater than the maximum input voltage.
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www.ti.com SLVS519A − MAY 2004 − REVISED OCTOBER 2004 Where K is the frequency multiplier for the spread between fLC and fCO. K should be between 5 and 15, typically 10 for one decade difference. For a desired crossover of 20 kHz and a 22-µH inductor, the minimum value for the output capacitor is 288 µF. The selected output capacitor must be rated for a voltage greater than the desired output voltage plus one half the ripple voltage.
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www.ti.com SLVS519A − MAY 2004 − REVISED OCTOBER 2004 Figure 5. The measured closed loop crossover frequency of 19.95 kHz differs from the calculated value because the actual output filter capacitor component parameters differed slightly from the specified data sheet values.
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www.ti.com SLVS519A − MAY 2004 − REVISED OCTOBER 2004 + + Figure 26. 3.3-V Power Supply With Schottky Diode Figure 26 shows an application where a clamp diode is used in place of the low-side FET. The TPS54352−7 incorporates an integrated pull-down FET so that the circuit remains operating in continuous mode during light load operation. A 3-A, 40-V Schottky diode such as the Motorola MBRS340T3 or equivalent is recommended.
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www.ti.com SLVS519A − MAY 2004 − REVISED OCTOBER 2004 Figure 27 is an example of power supply sequencing using a TPS54356 (U1) to generate an output of 3.3 V, and a TPS54354 (U2) to generate a 1.8-V output. These output voltages are typical I/O and core voltages for microprocessors and FPGAs. In the circuit, the 3.3-V supply is designed to power up first. The PWRGD pin of U1 is tied to the ENA pin of U2 so that the 1.
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www.ti.com SLVS519A − MAY 2004 − REVISED OCTOBER 2004 + + + Figure 29. 3.3-V Power Supply with Panasonic SP Output Filter Capacitors In Figure 29, the TPS54356 shown with two 180-µF 4-V special polymer dielectric output filter capacitors(C2 and C5). C10 is a high frequency bypass capacitor and does not enter into the design equations.
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www.ti.com SLVS519A − MAY 2004 − REVISED OCTOBER 2004 MAXIMUM SWITCHING FREQUENCY vs INPUT VOLTAGE 800 800 600 500 TPS54355 400 TPS54354 300 TPS54353 TPS54352 200 100 IO > 0.5 A 0 200 TPS54356 600 500 400 300 TPS54354 TPS54353 200 TPS54352 100 Stop 5.0 TPS54352−6 Start 4.0 Stop 50 75 TJ = 25°C 8 7 6 5 4 3 100 125 150 0 5 TA − Free-Air Temperature − 5C 10 15 20 0 10 7.0 6.5 6.0 5.5 5.0 4.5 4.
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www.ti.com SLVS519A − MAY 2004 − REVISED OCTOBER 2004 ON RESISTANCE vs JUNCTION TEMPERATURE CURRENT LIMIT vs INPUT VOLTAGE PH VOLTAGE vs SINK CURRENT 2 150 6.0 VI = 12 V IO = 0.5 A TJ = 25°C 130 5.0 4.5 1.75 PH Voltage − V On Resistance − mW Current Limit − A 5.5 110 90 5.0 1.25 7.5 10.0 12.5 15.0 17.5 1 50 −50 −25 20.0 0 25 Figure 40 0.35 0.30 0.25 0.20 0.15 0.10 10 9 3.5 2.5 2 1.
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www.ti.com SLVS519A − MAY 2004 − REVISED OCTOBER 2004 POWER DISSIPATION vs FREE-AIR TEMPERATURE PD − Power Dissipation − W 2.5 2 θJA = 42.1°C/W 1.5 1 θJA = 191.9°C/W 0.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) TPS54352PWPR HTSSOP PWP 16 2000 330.0 12.4 TPS54353PWPR HTSSOP PWP 16 2000 330.0 TPS54354PWPR HTSSOP PWP 16 2000 330.0 TPS54355PWPR HTSSOP PWP 16 2000 TPS54356PWPR HTSSOP PWP 16 TPS54357PWPR HTSSOP PWP 16 6.9 5.6 1.6 8.0 12.0 Q1 12.4 6.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS54352PWPR HTSSOP PWP 16 2000 367.0 367.0 35.0 TPS54353PWPR HTSSOP PWP 16 2000 367.0 367.0 35.0 TPS54354PWPR HTSSOP PWP 16 2000 367.0 367.0 35.0 TPS54355PWPR HTSSOP PWP 16 2000 367.0 367.0 35.0 TPS54356PWPR HTSSOP PWP 16 2000 367.0 367.0 35.0 TPS54357PWPR HTSSOP PWP 16 2000 367.0 367.0 35.
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