Datasheet

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 
SLVS519A − MAY 2004 − REVISED OCTOBER 2004
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2
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during
storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
T
A
OUTPUT VOLTAGE PACKAGE PART NUMBER
1.2 V Plastic HTSSOP (PWP) TPS54352PWP
1.5 V Plastic HTSSOP (PWP) TPS54353PWP
−40°C to 85°C
1.8 V Plastic HTSSOP (PWP) TPS54354PWP
−40
°
C to 85
°
C
2.5 V Plastic HTSSOP (PWP) TPS54355PWP
3.3 V Plastic HTSSOP (PWP) TPS54356PWP
5.0 V Plastic HTSSOP (PWP) TPS54357PWP
(1)
The PWP package is also available taped and reeled. Add an R suffix to the device type (i.e. TPS5435xPWPR).
PACKAGE DISSIPATION RATINGS
(1)
PACKAGE
THERMAL IMPEDANCE
JUNCTION-TO-AMBIENT
T
A
= 25°C
POWER RATING
T
A
= 70°C
POWER RATING
T
A
= 85°C
POWER RATING
16-Pin PWP with solder(2) 42.1°C/W 2.36 1.31 0.95
16-Pin PWP without solder 151.9°C/W 0.66 0.36 0.26
(1)
See Figure 47 for power dissipation curves.
(2)
Test Board Conditions
1. Thickness: 0.062”
2. 3” x 3”
3. 2 oz. Copper traces located on the top and bottom of the PCB for soldering
4. Copper areas located on the top and bottom of the PCB for soldering
5. Power and ground planes, 1 oz. copper (0.036 mm thick)
6. Thermal vias, 0.33 mm diameter, 1.5 mm pitch
7. Thermal isolation of power plane
For more information, refer to TI technical brief SLMA002.