Datasheet

V
OUTMIN
+ 0.12
ǒǒ
V
INMAX
* I
OMIN
0.110
Ǔ
) V
D
Ǔ
*
ǒ
I
OMIN
R
L
Ǔ
* V
D
V
OUTMAX
+ 0.87
ǒǒ
V
INMIN
* I
OMAX
0.230
Ǔ
) V
D
Ǔ
*
ǒ
I
OMAX
R
L
Ǔ
* V
D
C6=
1
2 xFz2xR1p
R3=
1
2 xFz1xC7p
C7=
1
2 xFp1x(R1||R2)p
Fz2=2.5xF
LC
TPS5430
TPS5431
SLVS632E –JANUARY 2006–REVISED SEPTEMBER 2013 www.ti.com
(17)
The final pole is located at a frequency too high to be of concern. The second zero, Fz2 as defined by
Equation 17 uses 2.5 for the frequency multiplier. In some cases this may need to be slightly higher or lower.
Values in the range of 2.3 to 2.7 work well. The values for R1 and R2 are fixed by the 3.3-V output voltage as
calculated usingEquation 12. For this design R1 = 10 kΩ and R2 = 5.90 kΩ. With Fp1 = 401 Hz, Fz1 = 2876 Hz
and Fz2 = 10.3 kHz, the values of R3, C6 and C7 are determined using Equation 18, Equation 19, and
Equation 20:
(18)
(19)
(20)
For this design, using the closest standard values, C7 is 0.1 μF, R3 is 549 Ω, and C6 is 1500 pF. C4 is added to
improve load regulation performance. It is effectively in parallel with C6 in the location of the second pole
frequency, so it should be small in relationship to C6. C4 should be less the 1/10 the value of C6. For this
example, 150 pF works well.
For additional information on external compensation of the TPS5430, TPS5431 or other wide voltage range
devices, see SLVA237 Using TPS5410/20/30/31 With Aluminum/Ceramic Output Capacitors
ADVANCED INFORMATION
Output Voltage Limitations
Due to the internal design of the TPS5430, there are both upper and lower output voltage limits for any given
input voltage. The upper limit of the output voltage set point is constrained by the maximum duty cycle of 87%
and is given by:
(21)
Where
V
INMIN
= minimum input voltage
I
OMAX
= maximum load current
V
D
= catch diode forward voltage.
R
L
= output inductor series resistance.
This equation assumes maximum on resistance for the internal high side FET.
The lower limit is constrained by the minimum controllable on time which may be as high as 200 ns. The
approximate minimum output voltage for a given input voltage and minimum load current is given by:
(22)
Where
V
INMAX
= maximum input voltage
I
OMIN
= minimum load current
V
D
= catch diode forward voltage.
R
L
= output inductor series resistance.
This equation assumes nominal on resistance for the high side FET and accounts for worst case variation of
operating frequency set point. Any design operating near the operational limits of the device should be
carefully checked to assure proper functionality.
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