Datasheet

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TPS54240
www.ti.com SLVSAA6A –APRIL 2010–REVISED DECEMBER 2012
DETAILED DESCRIPTION (continued)
Figure 42. Plot of Synchronizing in ccm Figure 43. Plot of Synchronizing in dcm
Figure 44. Plot of Synchronizing in PSM
Power Good (PWRGD Pin)
The PWRGD pin is an open drain output. Once the VSENSE pin is between 94% and 107% of the internal
voltage reference the PWRGD pin is de-asserted and the pin floats. It is recommended to use a pull-up resistor
between the values of 10 and 100kΩ to a voltage source that is 5.5V or less. The PWRGD is in a defined state
once the VIN input voltage is greater than 1.5V but with reduced current sinking capability. The PWRGD will
achieve full current sinking capability as VIN input voltage approaches 3V.
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