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User's Guide

SLUU303A – JUNE 2008 – Revised SEPTEMBER 2008

Using the TPS51103EVM Integrated 3.3-V/5-V Power LDO

with Clock Output

This document includes information regarding absolute operating conditions, power-supply requirements,

and hardware configuration for the evaluation module. The electrical schematics and bill of materials are

also included for reference purposes. Throughout this document, the phrase evaluation module and the

abbreviation EVM are both synonymous with the TPS51103EVM.

Contents

1 Introduction ................................................................................................................... 2

2 TPS51103EVM Electrical Performance Specifications ................................................................. 3

3 Schematic ..................................................................................................................... 4

4 Test Setup .................................................................................................................... 5

5 Typical Characteristics ...................................................................................................... 9

6 EVM Assembly Drawings and Layout ................................................................................... 13

7 Bill of Materials ............................................................................................................. 14

List of Figures

1 TPS51103EVM Power Stage/Control Schematic........................................................................ 4

2 TPS51103EVM Recommended Test Setup .............................................................................. 6

3 5-V and 3.3-V Enable Configuration ...................................................................................... 7

4 Switchover Function Enabled .............................................................................................. 7

5 VREG5 Load Regulation .................................................................................................... 9

6 VREG3 Load Regulation .................................................................................................... 9

7 15V_OUT Load Regulation ................................................................................................. 9

8 VRTC3 Load Regulation .................................................................................................... 9

9 0-mA to 100-mA Load Step on 5-V Output ............................................................................. 10

10 0-mA to 100-mA Load Step on 3.3-V Output ........................................................................... 10

11 5.0-V Switch Over .......................................................................................................... 11

12 5.0-V Switch Over .......................................................................................................... 11

13 3.3-V Switch Over .......................................................................................................... 11

14 3.3-V Switch Over .......................................................................................................... 11

15 Clock Startup................................................................................................................ 12

16 Clock Steady ................................................................................................................ 12

17 TPS51103EVM Component Placement (Top View) ................................................................... 13

18 TPS51103EVM Top Copper (Top View) ................................................................................ 13

19 TPS51103EVM Bottom Copper (X-Ray View from Top) .............................................................. 14

List of Tables

1 Electrical Performance Specifications ..................................................................................... 3

2 Meters ......................................................................................................................... 5

3 Test Points .................................................................................................................... 8

8 TPS51103EVM Bill of Materials .......................................................................................... 14

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SLUU303A – JUNE 2008 – Revised SEPTEMBER 2008 Using the TPS51103EVM Integrated 3.3-V/5-V Power LDO with Clock Output 1

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Summary of content (16 pages)

PAGE 1
User's Guide SLUU303A – JUNE 2008 – Revised SEPTEMBER 2008 Using the TPS51103EVM Integrated 3.3-V/5-V Power LDO with Clock Output This document includes information regarding absolute operating conditions, power-supply requirements, and hardware configuration for the evaluation module. The electrical schematics and bill of materials are also included for reference purposes. Throughout this document, the phrase evaluation module and the abbreviation EVM are both synonymous with the TPS51103EVM.
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Introduction 1 www.ti.com Introduction The TPS51103EVM evaluation module (EVM) is an integrated power LDO solution platform for testing and evaluation of the TPS51103, an integrated LDO with switch-over circuit for notebook computers (TI Literature Number SLUS808) The EVM delivers 3.3-V and 5-V of output voltage at 100 mA. It also produces an always-on 3.3-V low-dropout (LDO) output at 5 mA. 1.1 Description The EVM generates 3.3-V and 5-V LDO output from a wide input range of 5.5 V to 28 V.
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TPS51103EVM Electrical Performance Specifications www.ti.com 2 TPS51103EVM Electrical Performance Specifications Table 1. Electrical Performance Specifications PARAMETER CONDITIONS MIN TYP MAX UNITS INPUT CHARACTERISTICS VIN Input voltage range 5.5 28 V OUTPUT1 (5V_OUT) Output voltage 5 Load regulation 0 A < IOUT1 < 100 mA, VIN = 12 V Output load current IOUT1 V 5% 0 Output overcurrent 100 160 mA OUTPUT1 (3.3V_OUT) Output voltage Load regulation 3.
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Schematic 3 www.ti.com Schematic Figure 1. TPS51103EVM Power Stage/Control Schematic Note: 4 For reference only; see the enclosed Bill of Materials for specific values. Using the TPS51103EVM Integrated 3.
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Test Setup www.ti.com 4 Test Setup 4.1 Recommended Test Equipment 4.1.1 Voltage Source 4.1.1.1 VIN The input voltage source, VIN, should be a variable dc source, capable of 1-A dc, between 0 V and 30 V. Connect VIN as shown in Figure 2. 4.1.1.2 VIN5 This voltage source is applied only when the switchover function is tested. The voltage source should be a variable dc source, capable of 1-A dc, between 0 V and 6 V . 4.1.1.3 VIN3.
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Test Setup 4.2 4.2.1 www.ti.com Equipment Setup Electrostatic Discharge Warning CAUTION Failure to observe proper ESD handling procedures may result in damage to the EVM components. Many of the components used in the assembly of the TPS51103EVM are susceptible to damage by electrostatic discharge (ESD). Customers are advised to observe proper ESD handling procedures when unpacking and handling the TPS51103EVM.
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www.ti.com 4.2.3 Test Setup Output Connections Configure the output connections in the following order. Step 1. Connect LOAD1 and LOAD2 to 5V_OUT and 3.3V_OUT, respectively. Set LOAD1 and LOAD2 to sink 0 A dc before VIN is applied. Step 2. Connect voltmeters V4-V7 as shown in Figure 2. 4.3 Startup and Test Procedure 1. Ensure that LOAD1 and LOAD2 are set to constant current mode and to sink 0 A dc. 2. Increase VIN (V1) from 0 V to 10 V dc. 5V_OUT (V4), 3.3V_OUT (V5), and 3.
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Test Setup 4.5 www.ti.com Test Points Several test points are located around the board. Table 3 lists these various test points and the respective uses of each. Table 3. Test Points TEST POINT LABEL 4.6 DESCRIPTION VIN Input voltage positive sense point GND_VIN Input voltage negative sense point VIN5 5-V input voltage for switch over VIN3.3 3.3-V input voltage for switch over 5V_OUT 5-V LDO output positive sense point GND_5V 5-V LDO output negative sense point 3.3V_OUT 3.
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Typical Characteristics www.ti.com 5 Typical Characteristics 5.1 Load Regulation Figure 5 through Figure 16 present typical performance graphs for the TPS51103EVM. Because actual performance data can be affected by measurement techniques and environmental variables, these curves are presented for reference only and may differ from actual field measurements. VREG5 OUTPUT VOLTAGE vs OUTPUT CURRENT VREG3 OUTPUT VOLTAGE vs OUTPUT CURRENT 3.31 5.00 VVREG5 – Output Voltage – V 20 V 12 V 4.96 3.
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Typical Characteristics 5.2 www.ti.com Transient Response VIN = 7 V IOUT (100 mA/div) VIN = 7 V IOUT (100 mA/div) 5V_OUT 20 mV/div) 3.3V_OUT 20 mV/div) 5V_OUT 20 mV/div) 3.3V_OUT 20 mV/div) t – Time – 400 ms/div Figure 9. 0-mA to 100-mA Load Step on 5-V Output 10 t – Time – 400 ms/div Figure 10. 0-mA to 100-mA Load Step on 3.3-V Output Using the TPS51103EVM Integrated 3.
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Typical Characteristics www.ti.com 5.3 Switchover Function 5V_OUT (1 V/div) VIN5 (1 V/div) 5V_OUT (1 V/div) VIN5 (1 V/div) t – Time – 200 ms/div Figure 11. 5.0-V Switch Over t – Time – 2 ms/div Figure 12. 5.0-V Switch Over VIN3.3 (1 V/div) 3.3V_OUT (1 V/div) 3.3V_OUT (1 V/div) VIN3.3 (1 V/div) t – Time – 200 ms/div Figure 13. 3.3-V Switch Over t – Time – 10 ms/div Figure 14. 3.3-V Switch Over SLUU303A – JUNE 2008 – Revised SEPTEMBER 2008 Using the TPS51103EVM Integrated 3.
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Typical Characteristics 5.4 www.ti.com Clock and 15V_OUT VIN5 (1 V/div) 5V_OUT (1 V/div) 5V_OUT (2 V/div) 15V_OUT (5 V/div) CLOCK (2 V/div) VIN5 (1 V/div) CLOCK (2 V/div) t – Time – 10 ms/div Figure 15. Clock Startup 12 t – Time – 4 ms/div Figure 16. Clock Steady Using the TPS51103EVM Integrated 3.
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EVM Assembly Drawings and Layout www.ti.com 6 EVM Assembly Drawings and Layout Figure 17 through Figure 19 show the design of the TPS51103EVM printed circuit board (PCB). This EVM was designed using a two-layer, 2-oz. copper-clad PCB with all components on the top side to allow the user to easily view, probe, and evaluate the TPS51103 control IC in a practical application.
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Bill of Materials www.ti.com Figure 19. TPS51103EVM Bottom Copper (X-Ray View from Top) 7 Bill of Materials Table 8. TPS51103EVM Bill of Materials REFDES R1, R2 VALUE SIZE PART NUMBER MFR Resistor, Chip, 1/16w, 1% 603 std 3138-2 Pin, Wiring Terminal 0.09(D) X 0.31 inch 3138-2-00-15-00Mill Max 00-080 C1, C2, C4 0.22 µF Capacitor, Ceramic, 50 V, X7R, ±10% 0603 std std C3, C5, C9, C13 1 µF Capacitor, Ceramic, 25 V, X5R, ±10% 0603 std std C6, C8 std 0.
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EVALUATION BOARD/KIT IMPORTANT NOTICE Texas Instruments (TI) provides the enclosed product(s) under the following conditions: This evaluation board/kit is intended for use for ENGINEERING DEVELOPMENT, DEMONSTRATION, OR EVALUATION PURPOSES ONLY and is not considered by TI to be a finished end-product fit for general consumer use. Persons handling the product(s) must have electronics training and observe good engineering practice standards.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.