Datasheet

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SLUS564C − JULY 2003 − REVISED OCTOBER 2008
4
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ELECTRICAL CHARACTERISTICS (continued)
T
A
= −40°C to 85°C, 4.5 V < V
IN
< 20 V, C
VIN
= 0.1 µF, C
VREG5
= 2.2 µF, C
REF_X
= 0.01 µF, PGOOD = 0.2 V, ENBLx = DDR = VIN,
INVx = COMPx, RSSTRTx = OPEN, TRIP1 = TRIP2 = VIN, LLx = GND, VBSTx = LLx+5, C
(OUTx_U, OUTx_D)
=1 nF, REG5_IN = 0V, GND =
OUTGNDx = 0 V, VO1_VDDQ = VO2 = 0 V (unless otherwise stated)
PARAMETER UNITMAXTYPMINTEST CONDITIONS
REF_X REFERENCE VOLTAGE
V
REF10
10-V reference voltage V
IN
= 14 V, I
OUT
= 0 A 8.5 10.0 11.0 V
V
LD10
Load regulation 0 mA ≤ I
OUT
≤ 2 mA, V
IN
= 18 V -12% -20%
V
LN10
Line regulation I
OUT
= 100 µA, 14 V≤V
IN
≤28 V 5%
V
REFVTT
VTT reference voltage
DDR = 0 V wrt VO1_VDDQ input divided by 2
V
VO1
= 2.5 V
1.5%
V
REFVTT
VTT reference load regulation 0 mA ≤ I
O
≤ 3 mA 0.75%
POWERGOOD COMPARATORS
V
THDUAL(PG)
PGOOD threshold (dual mode)
Undervoltage PGOOD 765 786 808
mV
V
THDUAL(PG
)
PGOOD threshold (dual mode)
Overvoltage PGOOD
892 920 945
mV
V
THDDR(PG)
PGOOD threshold (DDR)
Undervoltage PGOOD,
VO1_VDDQ = 2.5 V
1.12 1.14 1.16
V
V
THDDR(PG
)
PGOOD threshold (DDR)
Overvoltage PGOOD,
VO1_VDDQ = 2.5 V
1.28 1.31 1.33
V
T
PG(del)
PGOOD delay time
INVx > undervoltage PGOOD,
Delay time from SSTRTx > 1.5 V to PGOOD
going high
2048 clks
DIGITAL CONTROL INPUTS
V
IH
High-level input voltage, logic DDR, ENBL1, ENBL2, SKIP 2.2
V
V
IL
Low-level input voltage, logic DDR, ENBL1, ENBL2, SKIP 0.3
V
I
INLEAK
Logic input leakage current DDR, ENBL1, ENBL2, SKIP= 5 V |1.0| µA
VO1_VDDQ and VO2
R
VOUT
VOx sink impedance V
VOUTx
= 0.5 V, fault engaged 6 10 Ω
V
VOUTOK
VOx low restart voltage Fault condition removed, restart 0.25 0.32 0.40 V
V
VO2LEAK
VOx input leakage current DDR= VIN, VOx = 5 V |1.0| µA
R
VOUT
VO1_VDDQ input impedance DDR= 0 1.5 MΩ
UNDERVOLTAGE AND OVERVOLTAGE PROTECTION
V
OVPDUAL
OVP trip output threshold (dual) Sensed at INVx 945 970 1010 mV
V
OVPDDR
OVP trip output threshold (DDR) VO1_VDDQ = 2.5 V 1.31 1.36 1.41 V
T
OVP(del)
OVP propagation delay time
(1)
20 µs
V
UVPDUAL
UVP trip output threshold (dual) Sensed at INVx 510 553 595
mV
V
UVPDDR
UVP trip output threshold (DDR) VO1_VDDQ = 2.5 V 750 813 875
mV
T
UVP(del)
UVP propagation delay time 4096 clks
OVERCURRENT and INPUT VOLTAGE UVLO PROTECTION
I
TRIPSNK
TRIPx sink current V
TRIPx
= V
IN
− 100 mV, T
A
= 25°C 11 13 15
A
I
TRIPSRC
TRIPx source current V
TRIPx
= 100 mV, T
A
= 25°C 10 13 16
µA
TC
ITRIP
TRIP current temperature coeficient
(1)
T
A
= 25°C 4200
ppm/
°C
V
OCPHI
High-level OCP comparator offset voltage
(1)
0 |3.0|
mV
V
OCPLO
Low-level OCP comparator offset voltage
(1)
0 |5.0|
mV
V
VINUVLO
VIN UVLO trip threshold REF5V_IN = 4.8 V 3.7 3.9 4.1 V
V
VINHYS
VIN UVLO trip hysteresis 100 200 300 mV