Datasheet

GATESWCONQSW
PPPP ++=
f
GATE g(TOT) g SW
P Q V= ´ ´
( )
( )
2
2
RIPPLE
OUT
QSW(rms) OUT(max)
IN(min)
I
V
I I
V 12
æ ö
ç ÷
= ´ +
ç ÷
è ø
( )
2
2 2
RIPPLE
OUT OUT OUT OUT
CAP(RMS) OUT OUT OUT
IN IN IN IN
I
V V V V
I I I I 1
V 12 V V V
é ù
æ ö æ ö æ ö
ê ú
= - ´ + ´ + ´ ´ -
ç ÷ ç ÷ ç ÷
ê ú
è ø è ø è ø
ë û
RIPPLE
RIPPLE
V
100 mV
ESR 47m
I 2.1A
= = = W
( )
2
2
OUT STEP
OUT
OVER OUT
L I
2.5 H 8
C 222.2 F
2 V V 2 200mV 1.8 V
´
m ´
= = = m
´ ´ ´ ´
( )
( )
( )
( )
2
2
OUT STEP
OUT
UNDER MAX IN(min) OUT
L I
2.5 H 8
C 71.68 F
2 200mV 90% 10.8 V 1.8 V
2 V D V V
´
m ´
= = = m
´ ´ ´ -
´ ´ ´ -
TPS40195
www.ti.com SLUS720E –FEBRUARY 2007–REVISED JULY 2012
Output Capacitor, C
OUT
The capacitance value is selected to be greater than the largest value calculated from Equation 13 and
Equation 14.
(13)
(14)
(15)
From Equation 13, Equation 14 and Equation 15, the capacitance for C
OUT
should be greater than 223 μF and its
ESR should be less than 47 mΩ. Three 100-μF, 6.3-V, X5R ceramic capacitors are chosen. Each capacitor has
an ESR of 5 mΩ .
Input Capacitor, C
IN
The input capacitor is selected to handle the ripple current of the buck stage. A relatively large capacitance is
used to keep the ripple voltage on the supply line low. This is especially important were the supply line has a
high impedance. It is recommended that the supply line impedance be kept low. The input capacitor RMS current
can be calculated using Equation 16.
(16)
The RMS current in the input capacitor is 3.56 A. Two 22-μF, size 1206 capacitors using X7R material has a
typical dissipation factor of 5%. For a 22-μF capacitor at 300 kHz the ESR is approximately 5 mΩ. Two of these
capacitors are used in parallel. The power dissipation in each capacitor is less than 16 mW. A 470-μF, 25-V
electrolytic is added to maintain the voltage on the input rail.
Switching MOSFET, Q
SW
The following key parameters must be met by the selected MOSFET.
• Drain-to-source voltage, V
DS
, must be able to withstand the input voltage plus spikes that may be on the
switching node. For this design a V
DS
rating of between 25 V and 30 V is recommended.
(17)
For this design I
DD
should be greater than 4.1 A
• Gate source voltage, V
gs
, must be able to withstand the gate voltage from the control device. For the
TPS40195 this is 5 V.
Target efficiency for this design is 90%. Based on 1.8-V output and 10-A operating current this equates to a
power loss in the module of 1.8 W. The design allocates this power budget equally between the two power FETS
and the inductor The equations below are used to calculate the power loss, P
QSW
, in the switching MOSFET.
(18)
(19)
Copyright © 2007–2012, Texas Instruments Incorporated 23