Datasheet

f
DAC
OFF
SC
7 N
t
´
=
( )
( )
( )
ILIMH min
OUT max
DS(on) max
V
I
R
=
TPS40195
www.ti.com SLUS720E –FEBRUARY 2007–REVISED JULY 2012
• V
ILIMOFST
is the offset voltage of the low side current sense comparator, ±20 mV
• R
DS(on)
is the channel resistance of the low-side MOSFET (6)
The short circuit protection threshold for the high-side MOSFET is fixed at 550-mV typical, 400-mV minimum with
a 4000 ppm/°C temperature coefficient to help compensate for changes in the high side FET channel resistance
as temperature increases. This threshold is in place to provide a maximum current output in the case of a fault.
The maximum amount of current that can be sourced from a converter can be found by Equation 7.
where
• I
OUT(max)
is the maximum current that the converter is specified to source
• V
ILIMH(min)
is the short circuit threshold for the high-side MOSFET (400 mV)
• R
DS(on)max
is the maximum resistance of the high-side MOSFET (7)
If the required current from the converter is greater than the calculated I
OUT(max)
, a lower resistance high-side
MOSFET must be chosen.
The length of time between restart attmepts after an output fault can be found from Equation 8.
where
• N
DAC
is the number of 1-V DAC ramp cycles from Table 2.
• f
SW
is the switching frequency in Hz (8)
5-V Regulator
This device has an on board 5-V regulator that allows the parts to operate from a single voltage feed. No
separate 5-V feed to the part is required. This regulator requires a minimum of 1 μF of capacitance on the BP pin
for stability. A ceramic capacitor is suggested for this purpose. Noise performance can be improved by increasing
this capacitance to 4.7 μF when driving FETs with more than 25nC gate charge requirements.
This regulator can also be used to supply power to nearby circuitry, eliminating the need for a separate LDO in
some cases. If this pin is used for external loads, be aware that this is the power supply for the internals of the
TPS40195. While efforts have been made to reduce sensitivity, any noise induced on this line has an adverse
effect on the overall performance of the internal circuitry and shows up as increased pulse jitter, or skewed
reference voltage. Note that when the EN pin is pulled low, the BP regulator will be turned off and not available
to supply power to external loads.
The amount of power available from this pin varies with the size of the power MOSFETs that the drivers must
operate. Larger MOSFETs require more gate drive current and reduces the amount of power available on this pin
for other tasks.
Pre-Bias Startup
The TPS40195 contains a unique circuit to prevent current from being pulled from the output during startup in the
condition the output is pre-biased. When the soft-start commands a voltage higher than the pre-bias level
(internal soft-start becomes greater than feedback voltage [V
FB
]), the controller slowly activates synchronous
rectification by starting the first LDRV pulses with a narrow on-time. It then increments that on-time on a cycle-
by-cycle basis until it coincides with the time dictated by (1-D), where D is the duty cycle of the converter. This
scheme prevents the initial sinking of the pre-bias output, and ensures that the out voltage (V
OUT
) starts and
ramps up smoothly into regulation and the control loop is given time to transition from pre-biased startup to
normal mode operation with minimal disturbance to the output voltage. The amount of time from the start of
switching until the low-side MOSFET is turned on for the full 1-D interval is defined by 32 clock cycles.
Copyright © 2007–2012, Texas Instruments Incorporated 17