Datasheet

R
DS(on)Q2
+
P
Q2C(on)
ǒ
I
L(rms)
Ǔ
2
ǒ
1 *
V
OUT
V
IN
Ǔ
R
DS(on)Q1
+
P
Q1C(on)
ǒ
I
L(rms)
Ǔ
2
V
OUT
V
IN
P
G1COM
+
ǒ
I
OUT
1
12
I
RIPPLE
Ǔ
2
R
DS(on)
D + I
L(rms)
R
DS(on)Q1
V
OUT
V
IN
Q
GD1
t
P
G1SW
V
IN
I
OUT
V
DD
* V
T
RDRV
1
f
SW
P
G1_SW
+
1
2
V
IN
I
OUT
T
SW
f
SW
+
1
2
V
IN
I
OUT
Q
GD1
V
DD
*V
TH
R
DRV
f
SW
TPS40192, TPS40193
SLUS719E –MARCH 2007–REVISED MAY 2013 www.ti.com
(17)
For this design switching losses will be highest at high-line Designing for 1 W of total losses in each MOSFETS
and 60% of the total high-side FET losses in switching losses, we can estimate our maximum gate-drain charge
for the design by using Equation 18.
(18)
For a 2-V gate threshold MOSFET, the TPS40192's 5-V gate drive, and the TPS40192's 2.5-Ω drive resistance,
we estimate a maximum gate-to-drain charge of 8.5 nC. The switching losses of the synchronous rectifier are
lower than the switching losses of the main FET because the voltage across the FET at the point of switching is
reduced to the forward voltage drop across the body diode of the SR FET and are estimated by using
Equation 19.
The conduction losses in the main FET are estimated by the RMS current through the FET times its R
DS(on)
.
(19)
Estimating about 40% of total MOSFET losses to be high-side conduction losses, the maximum R
DS(on)
of the
high-side FET can be estimated by using Equation 20.
(20)
For this design with I
L_RMS
= 11.22 A
RMS
and 8 V to 1.8 V design, calculate R
DS(on)Q1
< 17.3 mΩ for our main
switching FET.
Estimating 80% of total low-side MOSFET losses in conduction losses, repeat the calculation for the
synchronous rectifier, whose losses are dominated by the conduction losses. Calculate the maximum R
DS(on)
of
the synchronous rectifier by Equation 21.
(21)
For this design I
L(RMS)
= 10.22 A at V
IN
= 14 V to 1.8 V R
DS(on)Q2(max)
= 8.8 mΩ.
Table 5. Inductor Requirements V
IN
= 4.5 V
PARAMETER SYMBOL VALUE UNITS
High-side MOSFET on-resistance R
DS(on)
17.3 mΩ
High-side MOSFET gate-to-drain Q
GD1
8.5 nC
charge
Low-side MOSFET on-resistance R
DS(on)Q2
8.8 mΩ
The IRF7466 has an R
DS(on)MAX
of 17 mΩ at 4.5-V gate drive and only 8.0-nC V
GD
"Miller" charge with a 4.5-V
gate drive, and is chosen as a high-side FET. The IRF7834 has an R
DS(on)MAX
of 5.5 mΩ at 4.5-V gate drive and
44 nC of total gate charge. These two FETs have maximum total gate charges of 23 nC and 44 nC respectively,
which draws 40.2-mA from the 5-V regulator, less than its 50-mA minimum rating.
22 Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated
Product Folder Links: TPS40192 TPS40193